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For many systems, an execution scheduling model based on a timer interrupt is not sufficient to ensure a real-time response to external events. The C280x Hardware Interrupt block addresses this problem by allowing asynchronous processing of interrupts triggered by events managed by other blocks in the C280x DSP Chip Support Library.
The following C280x blocks that can generate an interrupt for asynchronous processing are available in Target Support Package™ TC2.
C280x ADC
C280x eCAN Receive
C280x SCI Receive
C280x SCI Transmit
C280x SPI Receive
C280x SPI Transmit
Only one Hardware Interrupt block can be used in a model. To handle multiple interrupts, place a Demux block at the output of the Hardware Interrupt block to direct function calls to the appropriate function-call subsystems.
The output of this block is a function call. The size of the function call line equals the number of interrupts the block is set to handle. Each interrupt is represented by four parameters shown on the dialog box of the block. These parameters are a set of four vectors of equal length. Each interrupt is represented by one element from each parameter (four elements total), one from the same position in each of these vectors.
Each interrupt is described by:
CPU interrupt numbers
PIE interrupt numbers
Task priorities
Preemption flags
So one interrupt is described by a CPU interrupt number, a PIE interrupt number, a task priority, and a preemption flag.
The CPU and PIE interrupt numbers together uniquely specify a single interrupt for a single peripheral or peripheral module. The following table maps CPU and PIE interrupt numbers to these peripheral interrupts.
C280x Peripheral Interrupt Vector Values
| Row numbers = CPU values / Column numbers = PIE values | ||||||||
|---|---|---|---|---|---|---|---|---|
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
| 1 | WAKEINT (LPM/WD) | TINT0 (TIMER 0) | ADCINT (ADC) | XINT2 | XINT1 | Reserved | SEQ2INT (ADC) | SEQ1INT (ADC) |
| 2 | Reserved | Reserved | EPWM6_TZINT (ePWM6) | EPWM5_TZINT (ePWM5) | EPWM4_TZINT (ePWM4) | EPWM3_TZINT (ePWM3) | EPWM2_TZINT (ePWM2) | EPWM1_TZINT (ePWM1) |
| 3 | Reserved | Reserved | EPWM6_INT (ePWM6) | EPWM5_INT (ePWM5) | EPWM4_INT (ePWM4) | EPWM3_INT (ePWM3) | EPWM2_INT (ePWM2) | EPWM1_INT (ePWM1) |
| 4 | Reserved | Reserved | Reserved | Reserved | ECAP4_INT (eCAP4) | ECAP3_INT (eCAP3) | ECAP2_INT (eCAP2) | ECAP1_INT (eCAP1) |
| 5 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | EQEP2_INT (eQEP2) | EQEP1_INT (eQEP1) |
| 6 | SPITXINTD (SPI-D) | SPIRXINTD (SPI-D) | SPITXINTC (SPI-C) | SPIRXINTC (SPI-C) | SPITXINTB (SPI-B) | SPIRXINTB (SPI-B) | SPITXINTA (SPI-A) | SPIRXINTA (SPI-A) |
| 7 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
| 8 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | I2CINT1A (I2C-A) | I2CINT2A (I2C-A) |
| 9 | ECAN1INTB (CAN-B) | ECAN0INTB (CAN-B) | ECAN1INTA (CAN-A) | ECAN0INTA (CAN-A) | SCITXINTB (SCI-B) | SCIRXINTB (SCI-B) | SCITXINTA (SCI-A) | SCIRXINTA (SCI-A) |
| 10 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
| 11 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
| 12 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
The task priority indicates the relative importance tasks associated with the asynchronous interrupts. If an interrupt triggers a higher-priority task while a lower-priority task is running, the execution of the lower-priority task will be suspended while the higher-priority task is executed. The lowest value represents the highest priority. Note that the default priority value of the base rate task is 40, so the priority value for each asynchronously triggered task must be less than 40 in order for these tasks to actually cause the suspension of the base rate task.
The preemption flag determines whether a given interrupt is preemptable. Preemption overrides prioritization, such that a preemptable task of higher priority can be preempted by a non-preemptable task of lower priority.

Enter a vector of CPU interrupt numbers for the interrupts you want to process asynchronously.
See the table of C280x Peripheral Interrupt Vector Values for a mapping of CPU interrupt number to interrupt names.
Enter a vector of PIE interrupt numbers for the interrupts you want to process asynchronously.
See the table of C280x Peripheral Interrupt Vector Values for a mapping of CPU interrupt number to interrupt names.
Enter a vector of task priorities for the interrupts you want to process asynchronously.
See the discussion of this block's Vectorized Output for an explanation of task priorities.
Enter a vector of preemption flags for the interrupts you want to process asynchronously.
See the discussion of this block's Vectorized Output for an explanation of preemption flags.
Select this check box if you want to be able to test asynchronous interrupt processing in the context of your Simulink® software model.
Note Select this check box to enable you to test asynchronous interrupt processing behavior in Simulink software. |
Detailed information about interrupt processing is in TMS320x280x DSP System Control and Interrupts Reference Guide, Literature Number SPRU712B, available at the Texas Instruments™ Web site.
The following links refer to block reference pages require that Target Support Package TC2 is installed.
C280x/C2833x Software Interrupt Trigger,Idle Task
![]() | Blocks — Alphabetical List | C281x Hardware Interrupt | ![]() |
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