| Embedded IDE Link™ CC | |
Options on the block dialog box let you set features of code generation for your custom C2xxx, F28xx, C5xxx, and C6xxx processor-based board. Adding this block to your Simulink® software model provides access to the processor hardware settings you need to configure when you generate a project from a Simulink software model or you generate code from Real-Time Workshop® software to run on a processor or board.
Any model that you use to generate a project or that you develop for custom hardware must include this block. Simulink or Real-Time Workshop software returns an error message if a target preferences block is not present in your model when you try to generate projects or code.
Note This block must be in your model at the top level and not in a subsystem. It does not connect to any other blocks, but stands alone to set the target preferences for the model. Simulink software returns an error when your model does not include a target preferences block or has more than one. |
The processor and target options you specify on this block are:
Processor and board information
Memory mapping and layout
Allocation of the various code sections, such as compiler, DSP/BIOS™, and custom sections
Operating parameters for peripherals on c280x and c281x processors
Setting the options included in this dialog box results in identifying your processor to Real-Time Workshop software, Embedded IDE Link CC, and Simulink software. Setting the options also, configures the memory map for your processor. Both steps are essential for generating code for any board that is custom or explicitly supported, such as the C6711 DSK or the DM642 EVM.
Unlike most other blocks, you cannot open the block dialog box until you add the block to a model. When you open the block dialog, the block attempts to connect to your processor. It cannot make the connection when the block is in the library and returns an error message.
Note If you do not have Texas Instruments' Code Composer Studio™ software installed, you cannot open this block. |
Real-Time Workshop software provides the ability to generate code from a selected subsystem in a model. To generate code for custom C2xxx, C5xxx, or C6xxx processor-based hardware from a subsystem, the subsystem model must include a target preferences block.
This reference page section contains the following subsections:
Target preferences block dialog boxes provide tabbed access to the following panes with options you set for the processor and target board:
Board info — Select the processor, set the clock speed, and identify the target. In addition, Add new on this pane opens the New Processor dialog box.
Memory — Set the memory allocation and layout on the target processor (memory mapping).
Sections — Determine the arrangement and location of the sections on the target processor such as where to put the DSP/BIOS and compiler information.
DSP/BIOS — (Optional) Specify how to configure tasking features of DSP/BIOS.
Peripherals — (Only for C2xxx family processors) Specify how to configure the peripherals provided by C2xxx processors, such as the SPI_A, SPI_B, GPIO, or eCAP peripherals.
The following options appear on the Board Info pane for the C6000 Target Preferences dialog box.
Lets you enter the type of board you are targeting with the model. You can enter Custom to support any board that uses one of the processors on the Processor list, or enter the name of one of the supported boards, such as C6711DSK. If you are using one of the explicitly supported boards, choose the target preferences block for that board and this field shows the proper board type.
Lets you select the type of processor to use from the list. The processor you select determines the contents and setting for options on the Memory and Sections panes in this dialog box. This selection controls the Operating system option. Selecting a processor that supports DSP/BIOS, such as a C6416, enables Operating system. If your processor does not support DSP/BIOS, such as the C2xxx processors, Operating system is disabled.
Clicking Add new opens a new dialog box where you specify configuration information for a processor that is not on the Processor list. Adding the new processor puts the new processor on the Processor list for all Target Preferences blocks, not just this one. The new processor and configuration become part of the available processors for all models that include a Target Preferences block.
For details about the New Processor dialog box, refer to New Processor Dialog Box.
Edit the configuration for the processor you select on the Processor list.
Delete a processor that you added to the Processor list. You cannot delete processors that you did not add.
Shows the clock speed of the processor on your target. When you enter a value, you are not changing the CPU clock rate. You are reporting the actual rate. If the value you enter does not match the rate on the target, your model's real-time results may be wrong, and the code profiling results are not correct.
Enter the actual clock rate the board uses. The rate you enter in this field does not change the rate on the board. Setting CPU clock speed to the actual board rate allows the code you generate to run correctly according to the actual clock rate of the hardware.
When you generate code for C6xxx processors from Simulink software models, you may encounter the software timer. The timer is invoked automatically to handle and create interrupts to drive your model when either of the following conditions occur:
Your model does not include ADC or DAC blocks
When the processing rates in your model change (the model is multirate)
Correctly generating interrupts for your model depends on the clock rate of the CPU on your target. You can change the rate with the DIP switches on the board or from one of the Texas Instruments software utilities.
For the timer software to calculate the interrupts correctly, Embedded IDE Link CC needs to know the actual clock rate of your target processor as you configured it. CPU clock speed lets you tell the timer the rate at which your target CPU runs, which is the rate to use to match the CPU rate.
The timer uses the CPU clock rate you specify in CPU clock speed to calculate the time for each interrupt. For example, if your model includes a sine wave generator block running at 1 kHz feeding a signal into an FIR filter block, the timer needs to create interrupts to generate the sine wave samples at the proper rate. Using the clock rate you choose, 100 MHz for example, the timer calculates the sine generator interrupt period as follows for the sine block:
Sine block rate = 1 kHz, or 0.001 s/sample
CPU clock rate = 100 MHz, or 0.000000001 s/sample
To create sine block interrupts at 0.001 s/sample requires:
100,000,000/1000 = 1 Sine
block interrupt per 100,000 clock ticks
Thus, you must report the correct clock rate, or the interrupts come at the wrong times and the results are incorrect.
Select this option when you are targeting a simulator rather than a hardware target. You must select Simulator to target your code to a C6xxx simulator.
Select this option to tell the code generation process to enable high-speed RTDX™ for this model.
Specify whether to use a real-time operating system (RTOS) with your model. Choose DSP/BIOS from the list to add the DSP/BIOS RTOS features to your project. Select None to disable the DSP/BIOS features.
You must have Target Support Package™ TC6 software installed to access this option.
Entries in this group specify the locations of custom source files or libraries or other functions. Options provide access to text areas where you enter files and file paths:
Source files — Enter the full paths to source code files to use with this target. By default there are no entries in this parameter.
Include paths — If you require additional files on your path, add them by typing the path into the text area. The default setting does not include additional paths.
Libraries — These entries identify specific libraries that the target requires. They appear on the list by default if required. Add more by entering the full path to the library with the library file in the text area. No additional libraries appear here in the default configuration.
Initialize functions — If your project requires an initialize function, enter it in this field. By default, this parameter is empty.
Terminate functions — Enter a function to run when a program terminates. The default setting is not to include a specific termination function.
Note When you enter a file path, library, or function, the block does not verify that the path or function exists or is valid. Invalid or incorrect entries in these fields may cause errors during code generation. |
To enter a path to a file, library, or other custom code, use the following string in the path to refer to the CCS installation directory.
$(install_dir)
Enter new paths or files (custom code items) one entry per line. Include the full path to the file for libraries and source code. Board custom code options do not support functions that use return arguments or values. Only functions of type void fname void are valid as entries in these parameters.
Contains a list of all the boards defined in CCS Setup. From the list of available boards, select the one that you are targeting.
Lists the processors on the board you selected for targeting in Board name. In most cases, only one name appears because the board has one processor. In the multiprocessor case, select the processor by name from the list.
When you target any board, you need to specify the layout of the physical memory on your processor and board to determine how use it for your program. For supported boards, the board-specific target preferences blocks set the default memory map.
The Memory pane contains memory options for three kinds of memory:
Physical Memory — Specifies the processor and board memory map
Heap — Specifies whether you use a heap and determines the size in words
Cache Configuration — Select a cache configuration where available, such as L2 cache, and select one of the corresponding configuration options, such as 32kb.
Be aware that these options may affect the options on the Sections pane. You can make selections here that change how you configure options on the Sections pane.
Most of the information about memory segments and memory allocation is available from the online help system for CCS.
This list shows the physical memory segments available on the board and processor. By default, target preferences blocks show the memory segments found on the selected processor. In addition, the Memory pane on preconfigured Target Preferences blocks shows the memory segments available on the board, but external to the processor. Target preferences blocks set default starting addresses, lengths, and contents of the default memory segments.
The default memory segments for each processor and board are different. For example:
Custom boards based on C670x processors provide IPRAM and IDRAM memory segments by default.
C671x processors provide IRAM memory segment by default.
When you highlight an entry on the Memory bank list list, the name of the entry appears in this field. To change the name of the existing memory segment, select it on Memory bank list and then type the new name in this field.
Note You cannot change the names of default processor memory segments. You can change the attributes of memory segments. |
To add a new physical memory segment to the list, click Add, replace the temporary label in Name with the one to use, and press Return. Your new segment appears on the list.
After you add the segment, you can configure the starting address, length, and contents for the new segment. New segments start with code and data as the type of content that can be stored in the segment (refer to the Contents option).
Names are case sensitive. NewSegment is not the same as newsegment or newSegment.
Address reports the starting address for the memory segment showing in Name. Address entries are in hexadecimal format and limited only by the board or processor memory.
From the starting address, Length sets the length of the memory allocated to the segment in Name. As in all memory entries, specify the length in hexadecimal format, in minimum addressable data units (MADUs). For the C6000 processor family, the MADU is 8 bytes, one word.
Contents details the kind of program sections that you can store in the memory segment in Name. As the processor type for the Target Preferences block changes, the kinds of information you store in listed memory segments may change. Generally, the Contents list contains these strings:
Code — Allow code to be stored in the memory segment in Name.
Data — Allow data to be stored in the memory segment in Name.
Code & Data — Allow code and data to be stored in the memory segment in Name. When you add a new memory segment, this is the default setting for the contents of the new element.
You may add or use as many segments of each type as you need, within the limits of the memory on your processor. Every processor must have sections that can hold code and data.
Click Add to add a new memory segment to the target memory map. When you click Add, a new segment name appears, for example NEWMEM1, in Name and on the Memory bank list list. In Name, change the temporary name NEWMEM1 by entering the new segment name. Entering the new name, or clicking Apply, updates the temporary name on the list to the name you enter.
This option lets you remove a memory segment from the memory map. Select the segment to remove on the Memory bank list list and click Remove to delete the segment.
Note To enable the Heap option, select DSP/BIOS for Operating system on the Board Info pane. |
If your processor supports using a heap, as the C6711 does, selecting this option enables creating the heap, and enables the Heap size option. Create heap is not available on processors that either do not provide a heap or do not allow you to configure the heap.
Using this option you can create a heap in any memory segment on the Memory bank list list. Select the memory segment on the list and then select Create heap to create a heap in the select segment. After you create the heap, use the Heap size and Define label options to configure the heap.
The location of the heap in the memory segment is not under your control. The only way to control the location of the heap in a segment is to make the segment and the heap the same size. Otherwise, the compiler determines the location of the heap in the segment.
After you select Create heap, this option lets you specify the size of the heap in words. Enter the number of words in decimal format. When you enter the heap size in decimal words, the system converts the decimal value to hexadecimal format. You can enter the value directly in hexadecimal format as well. Processors may support different maximum heap sizes.
Selecting Create heap enables this option that allows you to name the heap. Enter your label for the heap in the Heap label option.
Use this option, which you enable by selecting Define label, to provide the label for the heap. Any combination of characters is accepted for the label, except reserved characters in C/C++ compilers.
Note When you enter a label, the block does not verify that the label is valid. An invalid label in this field may cause errors during code generation. |
C621x, C671x, and C641x processors support an L2 cache memory structure that you can configure as SRAM and partial cache. Both the data memory and the program share this second-level memory. C620x DSPs do not support L2 cache memory and this option is not available when you choose one of the C620x processors as your target.
If your processor supports the two-level memory scheme, this option enables the L2 cache on the processor.
Some processor support code base memory organization. For example, a part of internal memory can be configure as code.
Cache level lets you select one of the available cache levels to configure by selecting one of its configurations. For example, you can select L2 cache level and choose one of its configurations, such as 32kB.
Options on this pane let you specify where various program sections should go in memory. Program sections are distinct from memory segments—sections are portions of the executable code stored in contiguous memory locations. Commonly used sections include .text, .bss, .data, and .stack. Some sections relate to the compiler and some can be custom sections.
For more information about program sections and objects, refer to the Code Composer Studio online help.
Within this pane, you configure the allocation of sections for Compiler, DSP/BIOS, and Custom needs.
This table provides brief definitions of the kinds of sections in the Compiler sections, DSP/BIOS sections/objects, and Custom sections lists in the pane. All sections do not appear on all lists. The list the string appears on is shown in the table.
String | Section List | Description of the Section Contents |
|---|---|---|
.args | DSP/BIOS | Argument buffers |
.bss | Compiler | Static and global C variables in the code |
.bios | DSP/BIOS | DSP/BIOS code if you are using DSP/BIOS options in your program |
.cinit | Compiler | Tables for initializing global and static variables and constants |
.cio | Compiler | Standard I/O buffer for C programs |
.const | Compiler | Data defined with the C qualifier and string constants |
.data | Compiler | Program data for execution |
.far | Compiler | Variables, both static and global, defined as far variables |
.gblinit | DSP/BIOS | Load allocation of the DSP/BIOS startup initialization tables section |
.hwi | DSP/BIOS | Dispatch code for interrupt service routines |
.hwi_vec | DSP/BIOS | Interrupt Service Table |
.obj | DSP/BIOS | Configuration properties that the target program can read |
.pinit | Compiler | Load allocation of the table of global object constructors section |
.rtdx_text | DSP/BIOS | Code sections for the RTDX program modules |
.stack | Compiler | The global stack |
.switch | Compiler | Jump tables for switch statements in the executable code |
.sysdata | DSP/BIOS | Data about DSP/BIOS |
.sysinit | DSP/BIOS | DSP/BIOS initialization startup code |
.sysmem | Compiler | Dynamically allocated object in the code containing the heap |
.text | Compiler | Load allocation for the literal strings, executable code, and compiler generated constants |
.trcdata | DSP/BIOS | TRC mask variable and its initial value section load allocation |
You can learn more about memory sections and objects in your Code Composer Studio online help.
When you highlight a section on the list, Description show a brief description of the section. Also,Placement shows you where the section is presently allocated in memory.
Provides a brief explanation of the contents of the selected entry on the Compiler sections list.
Shows you where the selected Compiler sections list entry is allocated in memory. You change the memory allocation by selecting a different location from the Placement list. The list contains the memory segments as defined in the physical memory map on the Memory pane. Select one of the listed memory segments to allocate the highlighted compiler section to the segment.
When your program uses code or data sections that are not included in either the Compiler sections or DSP/BIOS sections lists, you add the new sections to this list. Initially, the Custom sections list contains no fixed entries, but instead, only a placeholder for a section for you to define.
You enter the name for your new section here. To add a new section, click Add. Then, replace the temporary name with the name to use. Although the temporary name includes a period at the beginning you do not need to include the period in your new name. Names are case sensitive. NewSection is not the same as newsection, or newSection.
With your new section added to the Name list, select the memory segment to which to add your new section. Within the restrictions imposed by the hardware and compiler, you can select any segment that appears on the list.
Clicking Add lets you configure a new entry to the list of custom sections. When you click Add, the block provides a new temporary name in Name. Enter the new section name to add the section to the Custom sections list. After typing the new name, click Apply to add the new section to the list. You can also click OK to add the section to the list and close the dialog box.
To remove a section from the Custom sections list, select the section and click Remove.
Selecting DSP/BIOS for Operating system on the Board Info pane enables this pane.
To enable the DSP/BIOS pane, you must have installed Target Support Package TC6 and you must select DSP/BIOS from the Operating system list on the Board Info pane.
Options on this pane let you specify how to configure various modules of DSP/BIOS.
When you set the Operating system option to None, you disable the options in this pane.
For more information about tasks, refer to the Code Composer Studio online help.
Within this pane, you configure the options for DSP/BIOS tasks.
During program compilation, DSP/BIOS produces both uninitialized and initialized blocks of data and code. These blocks get allocated into memory as required by the configuration of your system. On the DSP/BIOS sections list you find both initialized (sections that contain data or executable code) and uninitialized (sections that reserve space in memory) sections.
Provides a brief explanation of the contents of the selected DSP/BIOS sections list entry.
Shows where the selected DSP/BIOS sections/objects list entry is allocated in memory. You change the memory allocation by selecting a different location from the Placement list. The list contains the memory segments available on C6000 processors and changes based on the processor you are using.
Distinct from the entries on the DSP/BIOS sections list, DSP/BIOS objects like STS or LOG, if your project uses them, get placed in the memory segment you select from the DSP/BIOS Object Placement list. All DSP/BIOS objects use the same memory segment. You cannot select the location for individual objects.
Specify where to place new data objects in memory.
Specify where to place new code objects in memory.
DSP/BIOS uses a stack to save and restore variables and CPU context during thread preemption for task threads. This option sets the size of the DSP/BIOS stack in bytes allocated for each task. 4096 bytes is the default value. You can set any size up to the limits for the processor. Set the stack size so that tasks do not use more memory than you allocate. While any task can use more memory than the stack includes, exceeding the stack memory size might cause the task to write into other memory or data areas, possibly causing unpredictable behavior.
Use this option to specify where to allocate the stack for static tasks. Static tasks are created whether or not they are needed for operation, compared to dynamic tasks that the system creates as needed. Tasks that your program uses often might be good candidates for static tasks. Infrequently used tasks usually work best as dynamic tasks.
The list offers IDRAM for locating the stack in memory. The Memory pane provides more options for the physical memory on the processor.
Like static tasks, dynamic tasks use a stack as well. Setting this option specifies where to locate the stack for dynamic tasks. In this case, MEM_NULL is the only valid stack location in memory. You must allocate system heap storage to use this option. Specify the system heap configuration on the Memory pane.
When you choose a C2000 processor from the Processor list on the Board info pane, this tabbed pane appears to let you configure peripheral settings and pin assignments.
You must have Target Support Package TC2 installed to enable this pane when you select a C2000 processor.
To set the attributes for a peripheral, select the peripheral from the Peripherals list and then set the attribute options on the right side.
The following table shows all of the peripherals provided on the Peripherals list. Some of the peripherals may not be available on some C2000 processors.
| Peripheral Name | Description |
|---|---|
| ADC | Report the settings for the analog-to-digital converter |
| SCI_A | Report or set the serial communications interface parameters for module A |
| SCI_B | Report or set the serial communications interface parameters for module B |
| SPI_A | Report or set the serial peripheral interface parameters for module A |
| SPI_B | Report or set the serial peripheral interface parameters for module B |
| SPI_C | Report or set the serial peripheral interface parameters for module C |
| SPI_D | Report or set the serial peripheral interface parameters for module D |
| eCAN_A | Report or set the eCAN parameters for module A |
| eCAN_B | Report or set the eCAN parameters for module B |
| eCAP | Report or assign eCAP module pins to general purpose IO pins if necessary |
| ePWM | Report or assign ePWM pins to general purpose IO pin if necessary |
The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK). The ADC operating clock speed is derived in several prescaler stages from the HSPCLK speed. For more information about configuring these scalers, refer to "Configuring ADC Parameters for Acquisition Window Width" in the Target Support Package TC2 documentation (available if you have installed Target Support Package TC2).
You can set the following parameters for the ADC clock prescaler:
This value does not actually have a direct effect on the ADC module's core clock speed. It serves to determine the width of the sampling or acquisition period. The higher the value, the wider is the sampling period. The default value is 4.
The HSPCLK speed is divided by this 4-bit value as the first step in deriving the ADC module's core clock speed. The default value is 3.
After the HSPCLK speed is divided by the ADCLKPS value, the result is further divided by 2 if the CPS parameter is set to 1, which is the default.
By default, an internally generated bandgap voltage reference is selected to supply the ADC logic. However, depending on application requirements, the ADC logic may be supplied by an external voltage reference. Choose True to use an external voltage reference.
The 280x ADC supports offset correction via a 9-bit value that is added or subtracted before the results are available in the ADC result registers. Timing for results is not affected. The default value is 0.
The serial communications interface parameters you can set for module A. These parameters are:
Baud rate for transmitting and receiving data. Select from 115200 (the default), 57600, 38400, 19200, 9600, 4800, 2400, 1200, 300, and 110.
If this option is set to True, system waits until data is available to read (when data length is reached). If this option is set to False, system checks FIFO periodically (in polling mode) to see if there is any data to read. If data is present, it reads and outputs the contents. If no data is present, it outputs the last value and continues.
Length in bits of each transmitted or received character, set to 8 bits.
Select Raw_data or Protocol mode. Raw data is unformatted and sent whenever the transmitting side is ready to send, whether the receiving side is ready or not. No deadlock condition can occur because there is no wait state. Data transmission is asynchronous. With this mode, it is possible the receiving side could miss data, but if the data is noncritical, using raw data mode can avoid blocking any processes.
When you select protocol mode, some handshaking between host and target occurs. The transmitting side sends $SND to indicate it is ready to transmit. The receiving side sends back $RDY to indicate it is ready to receive. The transmitting side then sends data and, when the transmission is completed, it sends a checksum.
Advantages to using protocol mode include:
Avoids deadlock
Ensures that data is received correctly (checksum)
Ensures that data is actually received by target
Ensures time consistency; each side waits for its turn to send or receive
Note Deadlocks can occur if one SCI Transmit block tries to communicate with more than one SCI Receive block on different COM ports when both are blocking (using protocol mode). Deadlocks cannot occur on the same COM port. |
Select Little Endian or Big Endian.
Select 8-bits or 16-bits.
Select this parameter to enable the loopback function for self-test and diagnostic purposes only. When this function is enabled, a C28x DSP's Tx pin is internally connected to its Rx pin and can transmit data from its output port to its input port to check the integrity of the transmission.
Select whether to use 1 or 2 stop bits.
Type of parity to use. Available selections are None, Odd parity, or Even parity. None disables parity. Odd sets the parity bit to one if you have an odd number of ones in your bytes, such as 00110010. Even sets the parity bit to one if you have an even number of ones in your bytes, such as 00110011.
Type of suspension to use when debugging your program with Code Composer Studio. When your program encounters a breakpoint, the suspension mode determines whether to perform the program instruction. Available options are Hard_abort, Soft_abort, and Free_run. Hard_abort stops the program immediately. Soft_abort stops when the current receive/transmit sequence is complete. Free_run continues running regardless of the breakpoint.
The serial communications interface parameters you can set for module B. These parameters are:
Baud rate for transmitting and receiving data. Select from 115200(the default), 57600, 38400, 19200, 9600, 4800, 2400, 1200, 300, and 110.
When you set this option to True, the system waits until data is available to read (when data length is reached). If this option is set to False, the system checks the FIFO periodically (in polling mode) to see if there is any data to read. If data is present, it reads and outputs the contents. If no data is present, the system outputs the last value and continues.
Length in bits of each transmitted/received character, set to 8 bits.
Select Raw_data or Protocol mode. Raw data is unformatted and sent whenever the transmitting side is ready to send, whether the receiving side is ready or not. No deadlock condition can occur because there is no wait state. Data transmission is asynchronous. With this mode, it is possible the receiving side could miss data, but if the data is noncritical, using raw data mode can avoid blocking any processes.
When you specify protocol mode, some handshaking between host and target occurs. The transmitting side sends $SND to indicate that it is ready to transmit. The receiving side sends back $RDY to indicate that it is ready to receive. The transmitting side then sends data and, when the transmission is completed, it sends a checksum.
Advantages to using protocol mode include:
Avoids deadlock
Ensures that data is received correctly (checksum)
Ensures that data is actually received by target
Ensures time consistency; each side waits for its turn to send or receive
Note Deadlocks can occur if one SCI Transmit block tries to communicate with more than one SCI Receive block on different COM ports when both are blocking (using protocol mode). Deadlocks cannot occur on the same COM port. |
Select Little Endian or Big Endian.
Select 8-bits or 16-bits.
Select this to enable the loopback function for self-test and diagnostic purposes only. When this function is enabled, the Tx pin on a C28x DSP is internally connected to its Rx pin and can transmit data from its output port to its input port to check the integrity of the transmission.
Select whether to use 1 or 2 stop bits.
Type of parity to use. Available selections are None, Odd parity, or Even parity. None disables parity. Odd sets the parity bit to one if you have an odd number of ones in your bytes, such as 00110010. Even sets the parity bit to one if you have an even number of ones in your bytes, such as 00110011.
Assigns the SCI receive something to a GPIO pin. Choices are None (default), GPI011, GPI015, GPI019, or GPI023.
Assigns the SCI transmit something to a GPIO pin. Choices are None (default), GPI09, GPI014, GPI018, or GPI022.
Type of suspension to use when debugging your program with Code Composer Studio. When your program encounters a breakpoint, the selected suspension mode determines whether to perform the program instruction. Available options are Hard_abort, Soft_abort, and Free_run. Hard_abort stops the program immediately. Soft_abort stops when the current receive or transmit sequence is complete. Free_run continues running regardless of the breakpoint.
The serial peripheral interface parameters you can set for the A module. These parameters are:
Factor to customize the baud rate, where the CPU rate is the target's working frequency and
Baud Rate = CPU Rate / (Baud Rate Factor + 1)
Select No_delay or Delay_half_cycle.
Select Rising_edge or Falling_edge.
Length in bits from 1 to 16 of each transmitted or received character. For example, if you select 8, the maximum data that can be transmitted using SPI is 28-1. If you send data greater than this value, the buffer overflows.
Select this option to enable the loopback function for self-test and diagnostic purposes only. When this function is enabled, the Tx pin on a C28x DSP is internally connected to its Rx pin and can transmit data from its output port to its input port to check the integrity of the transmission.
Set true or false.
Set level for receive FIFO interrupt. Select 0 through 16.
Set level for transmit FIFO interrupt. Select 0 through 16.
Enter FIFO transmit delay (in target clock cycles) to pause between data transmissions.
Set to Master or Slave.
Type of suspension to use when debugging your program with Code Composer Studio. When your program encounters a breakpoint, the selected suspension mode determines whether to perform the program instruction. Available options are Hard_abort, Soft_abort, and Free_run. Hard_abort stops the program immediately. Soft_abort stops when the current receive or transmit sequence is complete. Free_run continues running regardless of the breakpoint.
The serial peripheral interface parameters you can set for the B module. These parameters are:
Factor to customize the baud rate, where the CPU rate is the target's working frequency and
Baud Rate = CPU Rate / (Baud Rate Factor + 1)
Select No_delay or Delay_half_cycle.
Select Rising_edge or Falling_edge.
Length in bits from 1 to 16 of each transmitted or received character. For example, if you select 8, the maximum data that can be transmitted using SPI is 28-1. If you send data greater than this value, the buffer overflows.
Select this option to enable the loopback function for self-test and diagnostic purposes only. When this function is enabled, the Tx pin on a C28x DSP is internally connected to its Rx pin and can transmit data from its output port to its input port to check the integrity of the transmission.
Set true or false.
Set level for receive FIFO interrupt. Select 0 through 16.
Set level for transmit FIFO interrupt. Select 0 through 16.
Enter FIFO transmit delay (in seconds).
Set to Master or Slave.
Assigns the SPI something (CLK) to a GPIO pin. Choices are None (default), GPI014, or GPI026.
Assigns the SPI something (SIMO) to a GPIO pin. Choices are None (default), GPI012, or GPI024.
Assigns the SPI something (SOMI) to a GPIO pin. Choices are None (default), GPI013, or GPI025.
Assigns the SPI something (STE) to a GPIO pin. Choices areNone (default), GPI015, or GPI027.
Type of suspension to use when debugging your program with Code Composer Studio. When your program encounters a breakpoint, the selected suspension mode determines whether to perform the program instruction. Available options are Hard_abort, Soft_abort, and Free_run. Hard_abort stops the program immediately. Soft_abort stops when the current receive or transmit sequence is complete. Free_run continues running regardless of the breakpoint.
Parameters for the SPI_C module include all the parameters for the SPI_A module.
Parameters for the SPI_D module include all the parameters for the SPI_A module.
Each pin selected for input offers three signal qualification types:
Sync to SYSCLKOUT — This setting is the default for all pins at reset. Using this qualification type, the input signal is synchronized to the system clock SYSCLKOUT. The following figure shows the input signal measured on each tick of the system clock, and the resulting output from the qualifier.
Qualification using 3 samples — This setting requires three consecutive cycles of the same value for the output value to change. The following figure shows that, in the third cycle, the GPIO value changes to 0, but the qualifier output is still 1 because it waits for three consecutive cycles of the same GPIO value. The next three cycles all have a value of 0, and the output from the qualifier changes to 0 immediately after the third consecutive value is received.
Qualification using 6 samples — This setting requires six consecutive cycles of the same GPIO input value for the output from the qualifier to change. In the following figure, the glitch A has no effect on the output signal. When the glitch occurs, the counting begins, but the next measurement is low again, so the count is ignored. The output signal does not change until six consecutive samples of the high signal are measured.
A qualification sampling period prescaler in the Target Preferences block affects the preceding settings. For an illustrated explanation, refer to the entry Qualification sampling period prescaler.
Visible only when an appropriate setting for Qualification type for GPIO [pin#] is selected. The qualification sampling period prescaler, with possible values of 0 to 255, calculates the frequency of the qualification samples or the number of system clock ticks per sample. The formula for calculating the qualification sampling frequency is:
with the exception of zero. When Qualification sampling period prescaler=0, a sample is taken every SYSCLKOUT clock tick. For example, a prescale setting of 0 means that a sample is taken on each SYSCLKOUT tick.
The following figure shows the SYSCLKOUT ticks, a sample taken every clock tick, and the Qualification type set to Qualification using 3 samples. In this case, the Qualification sampling period prescaler=0:
In the next figure Qualification sampling period prescaler=1. A sample is taken every two clock ticks, and the Qualification type is set to Qualification using 3 samples. The output signal changes much later than if Qualification sampling period prescaler=0.
In the following figure, Qualification sampling period prescaler=2. Thus , a sample is taken every four clock ticks, and the Qualification type is set to Qualification using 3 samples.
For more help on setting the timing parameters for the eCAN modules, refer to Configuring Timing Parameters for CAN Blocks. You can set the following parameters for the eCAN module:
Value by which to scale the bit rate. Valid values are from 1 to 256.
Whether to use the CAN module in extended mode, which provides additional mailboxes and time stamping. The default is True. Selecting False enables only standard mode.
Number of samples used by the CAN module to determine the CAN bus level. Selecting Sample_one_time samples once at the sampling point. Selecting Sample_three_times samples once at the sampling point and twice before at a distance of TQ/2. A majority decision is made from the three points.
Sets the message resynchronization triggering. Options are Only_falling_edges and Both_falling_and_rising_edges.
Sets the synchronization jump width, which determines how many units of TQ a bit is allowed to be shortened or lengthened when resynchronizing.
If this parameter is set to True, the eCAN module goes to loopback mode, where a "dummy" acknowledge message is sent back without needing an acknowledge bit. The default is False.
Sets the value of time segment 1, which, with TSEG2 and Baud rate prescaler, determines the length of a bit on the eCAN bus. Valid values for TSEG1 are from 1 through 16.
Sets the value of time segment 2, which, with TSEG1 and Baud rate prescaler, determines the length of a bit on the eCAN bus. Valid values for TSEG2 are from 1 through 8.
The parameters you can set for the eCAN_B module include all the parameters for the eCAN_A module plus the following parameters which apply only when you use the eCAN_B module:
Assigns the CAN receive pin to use with the eCAN_B module. Possible values are GPIO10, GPIO13, GPIO17, and GPIO21.
Assigns the CAN transmit pin to use with the eCAN_B module. Possible values are GPIO8, GPIO12, GPIO16, and GPIO20.
Assigns eCAP pins to GPIO pins if required.
Select an option from the list—None, GPIO5, or GPIO24.
Select an option from the list—None, GPIO7, or GPIO25.
Select an option from the list—None, GPIO9, or GPIO26.
Select an option from the list—None, GPIO11, or GPIO27.
Assigns ePWM signals to GPIO pins, if required.
Assigns the ePWM external sync pulse input (SYNCI) to a GPIO pin. Choices are None (the default), GPIO6, and GPIO32.
Assigns the ePWM external sync pulse output (SYNCO) to a GPIO pin. Choices are None (the default), GPIO6, and GPIO33.
Assigns the trip-zone input 5 (TZ5) to a GPIO pin. Choices are None (the default), GPIO16, and GPIO28.
Assigns the trip-zone input 6(TZ6) to a GPIO pin. Choices are None (the default), GPIO17, and GPIO29.
When you click Add new on the General pane, you open this new dialog box to add a new processor to the list of supported processors.
The first time you click Save to add a new processor definition to the list of supported processors, a dialog box opens that directs you to select a destination folder for the saved processor definitions file customChipInfo.dat. You must select a directory to which you have write access. The location you specify becomes part of your MATLAB preferences. Future processors that you add become entries in the file customChipInfo.dat.
To add a new processor, you must enter values for the following parameters:
Name
Provide a name to identify your new processor. Any valid C string works here. The name you enter in this field appears on the list of processors after you add the new processor.
Processor Class
CPU clock
Enter the clock speed of the processor on your target in MHz. When you enter a value, you are not setting the CPU clock rate on the processor. You are reporting the rate. If the value you enter does not match the rate on the target, your model's real-time results may be wrong, and code profiling results are not correct.
Setting CPU clock to the actual board rate allows the code you generate to run correctly according to the actual clock rate of the hardware.
Define internal memory banks (one or more memory banks in)
Define default sections (one or more default sections)
If you do not provide an entry for each of these parameters, Embedded IDE Link CC returns an error message and does not create the new processor entry.
Provide a name to identify your new processor. You can use any valid C string value in this field. The name you enter in this field appears on the list of processors after you add the new processor.
Identifies the class of the new processor. Your new processor must be a member of a family of processors that Embedded IDE Link CC supports. For example, you can add a new C67xx processor because the product supports the C6700 processor family.
Generally, processors in a family share common design elements such as interrupt architecture and clock. They may have different memory maps. By selecting the processor class, you identify the common features of the processor family. The parameters in Define internal memory banks and Define default sections enable you to specify the memory mapping for your new processor.
For example, to add a new C2811 processor, enter the string 28xx. The following table lists the processor class string for supported processor families.
| Processor Family | Processor Class String |
|---|---|
| C62xx | 62xx where xx designates the processor, such as C6203. |
| C64xx | 64xx where xx designates the processor, such as C6412. Use 645x for the TCI6482. |
| C67xx | 67xx where xx designates the processor, such as C6722. |
| DM64x and DM64xx | 64xx where xx designates the processor, such as DM6433 or DM643. |
| C55xx | 55xx where xx designates the processor, such as C5502. For C5503, C5507, and C5509 processors, use 55xx. |
| C28xx, F28xx, R28xx, F28xxx | 28xx where xx designates the processor, such as C2812. For F283xx processors, use 2833x. For F280xx processors, use 280x. |
Provide a name to identify your new processor. You can use any valid C string value in this field. The name you enter in this field appears on the list of processors after you add the new processor.
Enter the clock speed of the processor in MHz. When you enter a value, you are not setting the CPU clock rate on the processor. You are reporting the rate. If the value you enter does not match the rate on the processor, your model's real-time results may be wrong, and code profiling results are not correct.
Setting CPU clock to the actual board rate allows the generated code to run correctly according to the actual clock rate of the hardware.
Identifies the processor family of the new processor to the compiler. Successful compilation requires this switch. The string depends on the processor family or class. For example, to set the compiler switch for a new C5509 processor, enter -ml. The following table shows the compiler switch string for supported processor families.
| Processor Family | Compiler Switch String |
|---|---|
| C62xx | None |
| C64xx | None |
| C67xx | None |
| DM64x and DM64xx | None |
| C55xx | -ml |
| C28xx, F28xx, R28xx, F28xxx | -ml |
This string specifies a prefix to add when the code generation process calls certain hook functions. The hook allows the code to call into handling functions that are specific to the processor selected. The following table shows the Code Generation hook string for supported processor families.
| Processor Family | Code Generation Hook String |
|---|---|
| C62xx | C6000 |
| C64xx | C6000 |
| C67xx | C6000 |
| DM64x and DM64xx | C6000 |
| C55xx | C5000 |
| C28xx, F28xx, R28xx, F28xxx | C2000 |
Parameters in this group configure the memory map for the new processor.
Parameters in this group configure the default sections for your new processor.
To add a new physical memory segment to the internal memory banks list, click Add, replace the temporary label in Name with the one to use, and press Return. Your new segment appears on the list.
After you add the segment, you can configure the starting address, length, and contents for the new segment. New segments start with code and data as the type of content that can be stored in the segment (refer to the Contents option).
Names are case sensitive. NewSegment is not the same as newsegment or newSegment.
Address reports the starting address for the memory segment showing in Name. Address entries are in hexadecimal format and limited only by the board or processor memory.
When you are using a processor-specific preferences block, the starting address shown is the default value. You can change the starting value by entering the new value directly in Address when you select the memory segment to change.
From the starting address, Length sets the length of the memory allocated to the segment in Name. As in all memory entries, specify the length in hexadecimal format, in minimum addressable data units (MADUs). For the C6000 processor family, for example, the MADU is 8 bytes, one word.
Contents details the kind of program sections that you can store in the memory segment in Name. As the processor type for the target preferences block changes, the kinds of information you store in listed memory segments may change. Generally, the Contents list contains these strings:
Code — Allow code to be stored in the memory segment in Name.
Data — Allow data to be stored in the memory segment in Name.
Code and Data — Allow code and data to be stored in the memory segment in Name. When you add a new memory segment, this setting is the default for the contents of the new element.
You may add or use as many segments of each type as you need, within the limits of the memory on your processor.
Click Add to add a new memory segment to the target memory map. When you click Add, a new segment name appears, for example NEWMEM1, in Name and on the list. In Name, change the temporary name NEWMEM1 by entering the new segment name. Entering the new name, or clicking OK updates the temporary name on the list to the name you enter.
This option lets you remove a memory segment from the memory map. Select the segment to remove from the list, and click Remove to delete the segment.
Enter the label for each option of the selected cache configuration, one label on each line, such as 0kb, 16kb, 32kb and so on.
Click Add to add a new cache configuration to the list. When you click Add, the new cache label appears on the list.
This option lets you remove a cache configuration from the cache list. Select the configuration to remove from the list, and click Remove to delete the cache.
Cache configurations and related options are defined as symbols to the project generator component. Cache options for new processors are not labeled until you add the labels.
Enter your label for the heap in the Label option. Entering the label updates the label of the selected configuration.
Options in this region let you specify where various program sections should go in memory and the contents and label for each section. You can add text to describe each section. Program sections are distinct from memory segments—sections are portions of the executable code stored in contiguous memory locations. Commonly used sections include .text, .bss, .data, and .stack. Some sections relate to the compiler, some to DSP/BIOS, and some can be custom sections as you require.
The name of the section corresponds to the symbolic name recognized by the linker program used with the respective processor.
Contents provides the information about the native of the program section. As the processor type for the target preferences block changes, the kinds of information you store in listed sections may change. Generally, the Contents list contains these strings:
Code — Allow code to be stored in the section in Name.
Data — Allow data to be stored in the section in Name.
Code and Data — Allow code and data to be stored in the section in Name. When you add a new section, this setting is the default for the contents.
You may add or use as many sections of each type as you need, within the limits of the memory on your processor.
Click Add to add a new section to the list. When you click Add, the new section appears on the list.
This option lets you remove a section from the section list. Select the section to remove from the list, and click Remove to delete the section.
Sections and related options are defined as symbols to the project generator component. Section options for new processors are not labeled until you add the labels.
The list on the left side of the pane shows the kinds of custom code you can specify for your processor. Each time you use your custom processor as defined in this dialog box, the custom code you enter here applies. You can enter custom code in the categories in the following table.
| Custom Code Entry | Description |
|---|---|
| Source files | Enter the full paths to source code files to use with this processor. By default there are no entries in this parameter. Enter each source file on a new line. |
| Include paths | If you require additional header files on your path, add them by typing the path into the text area, one file per line. The default setting does not include additional paths. |
| Libraries (Little Endian) | These entries identify specific little endian libraries that the target requires. Add more as you require by entering the full path to the library with the library file in the text area. Enter one library per line. No additional libraries appear in the default configuration. |
| Libraries (Big Endian) | These entries identify specific big endian libraries that the target requires. Add more as you require by entering the full path to the library with the library file in the text area. No additional libraries appear in the default configuration. Enter one library per line. |
| Preprocessor symbols | Enter any preprocessor symbols that the new processor requires for operation and compilation. No preprocessor symbols appear in the default configuration. Add the required symbols one symbol per line. |
You can use two types of tokens when you specify custom code paths:
$(Install_dir) — Refers to the installation directory of Code Composer Studio. One example of this token is
$(Install_dir) \c6000\csl\lib\csl6201.lib
$(MATLAB_ROOT) — Refers to the directory where you installed MATLAB.
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