Start the MATLAB application
and invoke the Cadence Incisive simulator (see Starting the HDL Simulator)
| | |
| | Create the HDL model.
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Compile and elaborate the HDL model using nclaunch. Load elaborated HDL model with EDA Simulator Link IN libraries.
See Loading an HDL Design for Verification.
| | |
| | | Create a new Simulink model. Add an HDL Cosimulation block (see Incorporating Hardware Designs into a Simulink Model). Define the block interface (see Defining the Block Interface). Add other Simulink blocks to complete the Simulink
model.
|
| | (Optional) Set breakpoints for interactive HDL debug.
| |
| | | Run the simulation. Verify that the revised model runs as expected. If
it does not, then: Modify the VHDL or Verilog code, and simulate it in
the HDL simulator. Determine whether you need to reconfigure the HDL Cosimulation block.
If you do, repeat steps 7 and 10.
Consider using a To VCD File block
to verify cosimulation results.
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