EDA Simulator Link™ IN

Introduction to Cosimulation

Creating a Hardware Model Design for Use in Simulink Applications

After you decide to include Simulink software as part of your EDA flow, think about how you will use it:

• Will you start by developing an HDL application using Cadence Incisive simulators, and possibly MATLAB software, and then test the results at a system level in Simulink?

• Will you start with a system-level model in Simulink with "black box hardware components" and, after the model runs as expected, replace the black boxes with HDL Cosimulation blocks?

• What other Simulink blocksets might apply to your application? Blocksets of particular interest for EDA applications include the Communications Blockset, Signal Processing Blockset, and Simulink Fixed Point software.

• Will you set up HDL Cosimulation blocks as a subsystem in your model?

• What sample times will be used in the model? Will any sample times need to be scaled?

• Will you generate a Value Change Dump (VCD) file?

After you answer these questions, use Simulink to build your simulation environment.

As the following figure shows, multiple cosimulation blocks in a Simulink model can request the service of multiple instances of the HDL simulator, using unique TCP/IP socket ports.

When you link the HDL simulator with a Simulink application, the simulator functions as the server. Using the EDA Simulator Link IN communications interface, an HDL Cosimulation block cosimulates a hardware component by applying input signals to and reading output signals from an HDL model under simulation in the HDL simulator.

This figure shows a sample Simulink model that includes an HDL Cosimulation block.

The HDL Cosimulation block models a Manchester receiver that is coded in HDL. Other blocks and subsystems in the model include the following:

• Frequency Error Range block, Frequency Error Slider block, and Phase Event block

• Manchester encoder subsystem

• Data alignment subsystem

• Inphase/Quadrature (I/Q) capture subsystem

• Error Rate Calculation block from the Communications Blockset software

• Bit Errors block

• Data Scope block

• Discrete-Time Scatter Plot Scope block from the Communications Blockset software

For information on getting started with Simulink software, see the Simulink online help or documentation.

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The EDA Simulator Link IN HDL Cosimulation Block

The EDA Simulator Link IN HDL Cosimulation Block links hardware components that are concurrently simulating in the HDL simulator to the rest of a Simulink model.

You can link Simulink and the HDL simulator in two possible ways:

• As a single HDL Cosimulation block fitted into the framework of a larger system-oriented Simulink model.

• As a Simulink model made up of a collection of HDL Cosimulation blocks, each representing a specific hardware component.

The block mask contains panels for entering port and signal information, setting communication modes, adding clocks, specifying pre- and post-simulation Tcl commands, and defining the timing relationship.

After you code one of your model's components in VHDL or Verilog and simulate it in the HDL simulator environment, you integrate the HDL representation into your Simulink model as an HDL Cosimulation block. This block, located in the Simulink Library, within the EDA Simulator Link IN block library, is shown in the next figure.

You configure an HDL Cosimulation block by specifying values for parameters in a block parameters dialog box. The HDL Cosimulation block parameters dialog box consists of tabbed panes that specify the following information:

• Ports Pane: Block input and output ports that correspond to signals, including internal signals, of your HDL design, and an output sample time. See Ports Pane in the Simulink Block Reference.

  

• Connection Pane: Type of communication and communication settings to be used for exchanging data between simulators. See Connection Pane in the Simulink Block Reference.

  

• Timescales Pane: The timing relationship between Simulink software and the HDL simulator. See Timescales Pane in the Simulink Block Reference.

  

• Clocks Pane: Optional rising-edge and falling-edge clocks to apply to your model. See Clocks Pane in the Simulink Block Reference.

  

• Tcl Pane: Tcl commands to run before and after a simulation. See Tcl Pane in the Simulink Block Reference.

  

Note   Verify that signals used in cosimulation have read/write access. You can check read/write access through the HDL simulator—see product documentation for details. This rule applies to all signals on the Ports, Clocks, and Tcl panes.

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Communication Between the HDL Simulator and Simulink Software

When you link the HDL simulator with a Simulink application, the simulator functions as the server, as shown in the following figure.

In this case, the HDL simulator responds to simulation requests it receives from cosimulation blocks in a Simulink model. You begin a cosimulation session from Simulink. After a session is started, you can use Simulink and the HDL simulator to monitor simulation progress and results. For example, you might add signals to a wave window to monitor simulation timing diagrams.

As the following figure shows, multiple cosimulation blocks in a Simulink model can request the service of multiple instances of the HDL simulator, using unique TCP/IP socket ports.

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Simulink Software-Cadence Incisive Workflow

Preparing for Cosimulation