| EDA Simulator Link™ IN | |
After you code one of your model's components in VHDL or Verilog and simulate it in the HDL simulator environment, integrate the HDL representation into your Simulink model as an HDL Cosimulation block by performing the following steps:
Open your Simulink model, if it is not already open.
Delete the model component that the HDL Cosimulation block is to replace.
In the Simulink Library Browser, click the EDA Simulator Link IN block library. The browser displays the HDL Cosimulation and To VCD block icons.
| HDL Cosimulation | Block that has at least one input port and one output port. |
| To VCD File | Generates a Value Change Dump (VCD) file. For information on using this block, see Adding a Value Change Dump (VCD) File. |
Copy the HDL Cosimulation block icon from the Library Browser to your model. Simulink creates a link to the block at the point where you drop the block icon.
Connect any HDL Cosimulation block ports to appropriate blocks in your Simulink model.
To model a sink device, configure the block with inputs only
To model a source device, configure the block with outputs only.
These rules are for signal/port and module path specifications in Simulink. Other specifications may work but are not guaranteed to work in this or future releases.
HDL designs generally do have hierarchy; that is the reason for this syntax. This specification does not represent a file name hierarchy.
Path specifications must follow these rules:
Path specification must start with a top-level module name.
Path specification can include "." or "/" path delimiters, but cannot include a mixture.
The leaf module or signal must match the HDL language of the top-level module.
The following examples show valid signal and module path specifications:
top.port_or_sig /top/sub/port_or_sig top top/sub top.sub1.sub2
The following examples show invalid signal and module path specifications:
top.sub/port_or_sig :sub:port_or_sig : :sub
Path specifications must follow these rules:
Path specification may include the top-level module name but it is not required.
Path specification can include "." or "/" path delimiters, but cannot include a mixture.
The leaf module or signal must match the HDL language of the top-level module.
The following examples show valid signal and module path specifications:
top.port_or_sig /sub/port_or_sig top top/sub top.sub1.sub2
The following examples show invalid signal and module path specifications:
top.sub/port_or_sig :sub:port_or_sig : :sub
You can creating rising-edge or falling-edge clocks, resets, or clock enable signals that apply internal stimuli to your model under cosimulation. You can add these signals in the following ways:
Add signals to your Simulink model using Simulink blocks.
In the following example excerpt, the shaded area shows a clock, a reset, and a clock enable signal as input to a multiple HDL Cosimulation block model. These signals are created using two Simulink data type conversion blocks and a constant source block
Add clocks using the Clocks pane of the HDL Cosimulation block. See Creating Optional Clocks with the Clocks Pane of the HDL Cosimulation Block.
Drive clocks, resets, and enable signals by adding force commands to the Tcl pane.
For example:
@force osc_top.clk_enable 1 -after 0ns @force osc_top.reset 0 -after 0ns 1 -after 40ns 0 -after 120ns @force osc_top.clk 1 -after 0ns 0 -after 40ns -repeat 80ns
Specify signals with the nclaunch and force commands.
For example:
nclaunch('tclstart',['-input "{@force osc_top.clk_enable 1 -after 0ns}"',
'-input "{@force osc_top.reset 0 -after 0ns 1 -after 40ns 0 -after 120ns}"',
'-input "{@force osc_top.clk 1 -after 0ns 0 -after 40ns -repeat 80ns}"']);Implement clocks, resets, and enable signals in HDL code. If your model is part of a much larger HDL design, you (or the larger model designer) may choose to implement these signals in the Verilog or VHDL files. However, that implementation exceeds the scope of this documentation; see an HDL reference for more information.
When you specify a clock in your block definition, Simulink creates a rising-edge or falling-edge clock that drives the specified HDL signals by depositing them.
Simulink attempts to create a clock that has a 50% duty cycle and a predefined phase that is inverted for the falling edge case. If necessary, Simulink degrades the duty cycle to accommodate odd Simulink sample times, with a worst case duty cycle of 66% for a sample time of T=3.
The following figure shows a timing diagram that includes rising and falling edge clocks with a Simulink sample time of T=10 and an HDL simulator resolution limit of 1 ns. The figure also shows that given those timing parameters, the clock duty cycle is 50%.
To create clocks, perform the following steps:
In the HDL simulator, determine the clock signal path names you plan to define in your block. To do so, you can use the same method explained for determining the signal path names for ports in step 1 of Mapping HDL Signals to Block Ports.
Select the Clocks tab of the Block Parameters dialog box. Simulink displays the dialog box as shown in the next figure.
Click New to add a new clock signal.
Edit the clock signal path name directly in the table under the Full HDL Name column. To do so, double-click the default clock signal name (/top/clk). Then, specify your new clock using HDL simulator path name syntax. See Specifying HDL Signal/Port and Module Paths for Cosimulation.
The HDL simulator does not support vectored signals in the Clocks pane. Signals must be logic types with 1 and 0 values.
To specify whether the clock generates a rising-edge or falling edge signal, select Rising or Falling from the Active Clock Edge list.
The Period field specifies the clock period. Accept the default (2), or override it by entering the desired clock period explicitly by double-clicking in the Period field.
Specify the Period field as an even integer, with a minimum value of 2.
When you have finished editing clock signals, click Apply to register your changes with Simulink.
The following dialog box defines the rising-edge clock clk for the HDL Cosimulation block, with a default period of 2.
To open the block parameters dialog box for the HDL Cosimulation block, double-click the block icon.
Simulink displays the following Block Parameters dialog box.
The first step to configuring your EDA Simulator Link IN Cosimulation block is to map signals and signal instances of your HDL design to port definitions in your HDL Cosimulation block. In addition to identifying input and output ports, you can specify a sample time for each output port. You can also specify a fixed-point data type for each output port.
The signals that you map can be at any level of the HDL design hierarchy.
To map the signals, you can perform either of the following actions:
Enter signal information manually into the Ports pane of the HDL Cosimulation Block Parameters dialog box (see Entering Signal Information Manually). This approach can be more efficient when you want to connect a small number of signals from your HDL model to Simulink.
Use the Auto Fill button to obtain signal information automatically by transmitting a query to the HDL simulator. This approach can save significant effort when you want to cosimulate an HDL model that has many signals that you want to connect to your Simulink model. However, in some cases, you will need to edit the signal data returned by the query. See Obtaining Signal Information Automatically from the HDL Simulator for details.
Note Verify that signals used in cosimulation have read/write access. You can check read/write access through the HDL simulator—see product documentation for details. This rule applies to all signals on the Ports, Clocks, and Tcl panes. |
Obtaining Signal Information Automatically from the HDL Simulator. The Auto Fill button lets you begin an HDL simulator query and supply a path to a component or module in an HDL model under simulation in the HDL simulator. Usually, some change of the port information is required after the query completes. The following example describes the required steps.
The example is based on a modified copy of the Manchester Receiver model (see Creating a Hardware Model Design for Use in Simulink Applications), in which all signals were first deleted from the Ports and Clocks panes.
Open the block parameters dialog box for the HDL Cosimulation block. Click the Ports tab. The Ports pane opens.
Click the Auto Fill button. The Auto Fill dialog box opens.
This modal dialog box requests an instance path to a component or module in your HDL model; here you enter an explicit HDL path into the edit field. The path you enter is not a file path and has nothing to do with the source files.
In this example, the Auto Fill feature obtains port data for a VHDL component called manchester. The HDL path is specified as /top/manchester.
Click OK to dismiss the dialog box and the query is transmitted.
After the HDL simulator returns the port data, the Auto Fill feature enters it into the Ports pane, as shown in the following figure.
Click Apply to commit the port additions.
The preceding figure shows that the query entered clock, clock enable, and reset ports (labeled clk, enable, and reset respectively) into the ports list. In this example, the clk signal is entered in the Clocks pane, and the enable and reset signals are deleted from the Ports pane, as the next figures show.
Auto Fill returns default values for output ports:
Sample time: 1
Data type: Inherit
Fraction length: Inherit
You may need to change these values as required by your model. In this example, the Sample time should be set to 10 for all outputs. See also Specifying the Signal Data Types.
Before closing the HDL Cosimulation block parameters dialog box, click Apply to commit any edits you have made.
Observe that Auto Fill returned information about all inputs and outputs for the targeted component. In many cases, this will include signals that function in the HDL simulator but cannot be connected in the Simulink model. You may delete any such entries from the list in the Ports pane if they are unwanted. You can drive the signals from Simulink; you just have to define their values by laying down Simulink blocks.
Note that Auto Fill does not return information for internal signals. If your Simulink model needs to access such signals, you must enter them into the Ports pane manually. For example, in the case of the Manchester Receiver model, you would need to add output port entries for top/manchester/sync_i, top/manchester/isum_i, and top/manchester/qsum_i, as shown in step 8.
Note When you import VHDL signals using Auto Fill, the HDL simulator returns the signal names in all capitals. |
Entering Signal Information Manually. To enter signal information directly in the Ports pane, perform the following steps:
In the HDL simulator, determine the signal path names for the HDL signals you plan to define in your block.
In Simulink, open the block parameters dialog box for your HDL Cosimulation block, if it is not already open.
Select the Ports pane tab. Simulink displays the following dialog box.
In this pane, you define the HDL signals of your design that you want to include in your Simulink block and set a sample time and data type for output ports. The parameters that you should specify on the Ports pane depend on the type of device the block is modeling as follows:
For a device having both inputs and outputs: specify block input ports, block output ports, output sample times and output data types.
For output ports, accept the default or enter an explicit sample time. Data types can be specified explicitly, or set to Inherit (the default). In the default case, the output port data type is inherited either from the signal connected to the port, or derived from the HDL model.
For a sink device: specify block output ports.
For a source device: specify block input ports.
Enter signal path names in the Full HDL name column by double-clicking on the existing default signal.
Use HDL simulator path name syntax (see Specifying HDL Signal/Port and Module Paths for Cosimulation).
If you are adding signals, click New and then edit the default values. Select either Input or Output from the I/O Mode column.
If you want to, set the Sample Time, Data Type, and Fraction Length parameters for signals explicitly, as discussed in the remaining steps.
When you have finished editing clock signals, click Apply to register your changes with Simulink.
The following dialog box shows port definitions for an HDL Cosimulation block. The signal path names match path names that appear in the HDL simulator wave window.
You must specify a sample time for the output ports. Simulink uses the value that you specify, and the current settings of the Timescales pane, to calculate an actual simulation sample time.
For more information on sample times in the EDA Simulator Link IN cosimulation environment, see Representation of Simulation Time.
You can configure the fixed-point data type of each output port explicitly if desired, or use a default (Inherited) . In the default case, Simulink determines the data type for an output port as follows:
If Simulink can determine the data type of the signal connected to the output port, it applies that data type to the output port. For example, the data type of a connected Signal Specification block is known by back-propagation. Otherwise, Simulink queries the HDL simulator to determine the data type of the signal from the HDL module.
To assign an explicit fixed-point data type to a signal, perform the following steps:
Select either Signed or Unsigned from the Data Type column.
If the signal has a fractional part, enter the Fraction Length.
For example, if the model has an 8-bit signal with Signed data type and a Fraction Length of 5, the HDL Cosimulation block assigns it the data type sfix8_En5. If the model has an Unsigned 16-bit signal with no fractional part (a Fraction Length of 0), the HDL Cosimulation block assigns it the data type ufix16.
Before closing the dialog box, click Apply to register your edits.
The Data Type and Fraction Length parameters apply only to output signals, as follows:
The Data Type property is enabled only for output signals. You can direct Simulink to determine the data type, or you can assign an explicit data type (with option fraction length). By explicitly assigning a data type, you can force fixed point data types on output ports of an HDL Cosimulation block.
The Fraction Length property specifies the size, in bits, of the fractional part of the signal in fixed-point representation. The Fraction Length property is enabled when the signal Data Type property is not set to Inherit.
The Data Type and Fraction Length properties apply only to the following signals:
VHDL signals of STD_LOGIC or STD_LOGIC_VECTOR type
Verilog signals of wire or reg type
Output port data types are determined by the signal width and by the Data Type and Fraction Length properties of the signal. To assign a port data type, set the Data Type and Fraction Length properties as follows:
Select Inherit from the Data Type list if you want Simulink to determine the data type.
Inherit is the default setting. When you select Inherit, the Fraction Length edit field is disabled.
Simulink attempts to compute the data type of the signal connected to the output port by backward propagation. For example, if a Signal Specification block is connected to an output, Simulink will force the data type specified by Signal Specification block on the output port.
If Simulink cannot determine the data type of the signal connected to the output port, it will query the HDL simulator for the data type of the port. As an example, if the HDL simulator returns the data type STD_LOGIC_VECTOR for a VHDL signal of size N bits, the data type ufixN is forced on the output port. (The implicit fraction length is 0.)
Select Signed from the Data Type list if you want to explicitly assign a signed fixed-point data type. When you select Signed , the Fraction Length edit field is enabled. The port is assigned a fixed point type sfixN_EnF, where N is the signal width and F is the Fraction Length.
For example, if you specify Data Type as Signed and a Fraction Length of 5 for a 16-bit signal, Simulink forces the data type to sfix16_En5. For the same signal with a Data Type set to Signed and Fraction Length of -5 , Simulink forces the data type to sfix16_E5.
Select Unsigned from the Data Type list if you want to explicitly assign an unsigned fixed point data type. When you select Unsigned, the Fraction Length edit field is enabled. The HDL Cosimulation block assigns the port a fixed point type ufixN_EnF, where N is the signal width and F is the Fraction Length value.
For example, if you specify Data Type as Unsigned and a Fraction Length of 5 for a 16-bit signal, Simulink forces the data type to ufix16_En5. For the same signal with a Data Type set to Unsigned and Fraction Length of -5 , Simulink forces the data type to ufix16_E5.
You configure the timing relationship between Simulink and the HDL simulator by using the Timescales pane of the block parameters dialog box. Before setting the Timescales parameters, you should read Representation of Simulation Time to understand the supported timing modes and the issues that will determine your choice of timing mode.
You can specify either a relative or an absolute timing relationship between Simulink and the HDL simulator, as described in Timescales Pane of the HDL Cosimulation block reference.
Configure a block's communication link with the Connection pane of the block parameters dialog box.
The following steps guide you through the communication configuration:
Determine whether Simulink and the HDL simulator are running on the same computer. If they are, skip to step 4.
Clear the The HDL simulator is running on this computer check box. (This check box defaults to selected.) Because Simulink and the HDL simulator are running on different computers, Connection method is automatically set to Socket.
Enter the host name of the computer that is running your HDL simulation (in the HDL simulator) in the Host name text field. In the Port number or service text field, specify a valid port number or service for your computer system. For information on choosing TCP/IP socket ports, see Choosing TCP/IP Socket Ports. Skip to step 5.
If the HDL simulator and Simulink are running on the same computer, decide whether you are going to use shared memory or TCP/IP sockets for the communication channel. For information on the different modes of communication, see Communicating with MATLAB or Simulink and the HDL Simulator.
If you choose TCP/IP socket communication, specify a valid port number or service for your computer system in the Port number or service text field. For information on choosing TCP/IP socket ports, see Choosing TCP/IP Socket Ports.
If you choose shared memory communication, select the Shared memory check box.
If you want to bypass the HDL simulator when you run a Simulink simulation, use the Connection Mode options to specify what type of simulation connection you want. Select one of the following options:
Full Simulation: Confirm interface and run HDL simulation (default).
Confirm Interface Only: Check HDL simulator for proper signal names, dimensions, and data types, but do not run HDL simulation.
No Connection: Do not communicate with the HDL simulator. The HDL simulator does not need to be started.
With the second and third options, EDA Simulator Link IN software does not communicate with the HDL simulator during Simulink simulation.
Click Apply.
The following example dialog box shows communication definitions for an HDL Cosimulation block. The block is configured for Simulink and the HDL simulator running on the same computer, communicating in TCP/IP socket mode over TCP/IP port 4449.
You have the option of specifying Tcl commands to execute before and after the HDL simulator simulates the HDL component of your Simulink model. Tcl is a programmable scripting language supported by most HDL simulation environments. Use of Tcl can range from something as simple as a one-line puts command to confirm that a simulation is running or as complete as a complex script that performs an extensive simulation initialization and startup sequence. For example, you can use the Post- simulation command field on the Tcl Pane is particularly to instruct the HDL simulator to restart at the end of a simulation run.
You can specify the pre-simulation and post-simulation Tcl commands by entering Tcl commands in the Pre-simulation commands or Post-simulation commands text fields of the HDL Cosimulation block.
To specify Tcl commands, perform the following steps:
Select the Tcl tab of the Block Parameters dialog box. The dialog box appears as follows.
The Pre-simulation commands text box includes an puts command for reference purposes.
Enter one or more commands in the Pre-simulation command and Post-simulation command text boxes. You can specify one Tcl command per line in the text box or enter multiple commands per line by appending each command with a semicolon (;), which is the standard Tcl concatenation operator.
Click Apply.
One way to control block parameters is through the HDL Cosimulation block graphical dialog box. However, you can also control blocks by programmatically controlling the mask parameter values and the running of simulations. Parameter values can be read using the Simulink get_param function and written using the Simulink set_param function. All block parameters have attributes that indicate whether they are:
Tunable — The attributes can change during the simulation run.
Evaluated — The parameter string value undergoes an evaluation to determine its actual value used by the S-Function.
The HDL Cosimulation block does not have any tunable parameters; thus, you get an error if you try to change a value while the simulation is running. However, it does have a few evaluated parameters.
You can see the list of parameters and their attributes by performing a right-mouse click on the block, selecting View Mask, and then the Parameters tab. The Variable column shows the programmatic parameter names. Alternatively, you can get the names programmatically by selecting the HDL Cosimulation block and then typing the following commands at the MATLAB prompt:
>> get_param(gcb, 'DialogParameters')
Some examples of using MATLAB to control simulations and mask parameter values follow. Usually, the commands are put into an M-script or M-function file and automatically called by several callback hooks available to the model developer. You can place the code in any of these suggested locations, or anywhere you choose:
In the model workspace, e.g., View > Model Explorer > Simulink Root > model_name > Model Workspace > Data Source is M-Code.
In a model callback, e.g., File > Model Properties > Callbacks.
A subsystem callback (right-mouse click on an empty subsystem and then select Block Properties > Callbacks). Many of the EDA Simulator Link IN demos use this technique to start the HDL simulator by placing M-code in the OpenFcn callback.
The HDL Cosimulation block callback (right-mouse click on HDL Cosimulation block, and then select Block Properties > Callbacks).
The following example shows the one way of programmatically controlling the HDL Cosimulation block parameters.
Scripting the Value of the Socket Number for HDL Simulator Communication. In a regression environment, you may need to determine the socket number for the Simulink/HDL simulator connection during the simulation to avoid collisions with other simulation runs. This example shows code that could handle that task. The script is for a 32-bit Linux platform.
ttcp_exec = [matlabroot '/toolbox/shared/hdllink/scripts/ttcp_glnx'];
[status, results] = system([ttcp_exec ' -a']);
if ~s
parsed_result = strread(results,'%s');
avail_port = parsed_result{2};
else
error(results);
end
set_param('MyModel/HDL Cosimulation', 'CommPortNumber', avail_port);
A value change dump (VCD) file logs changes to variable values, such as the values of signals, in a file during a simulation session. VCD files can be useful during design verification. Some examples of how you might apply VCD files include the following cases:
For comparing results of multiple simulation runs, using the same or different simulator environments
As input to post-simulation analysis tools
For porting areas of an existing design to a new design
VCD files can provide data that you might not otherwise acquire unless you understood the details of a device's internal logic. In addition, they include data that can be graphically displayed or analyzed with postprocessing tools.
For example, including the extraction of data about a particular section of a design hierarchy or data generated during a specific time interval.
The To VCD File block provided in the EDA Simulator Link IN block library serves as a VCD file generator during Simulink sessions. The block generates a VCD file that contains information about changes to signals connected to the block's input ports and names the file with a specified file name.
Note The To VCD File block logs changes to states '1' and '0' only. The block does not log changes to states 'X' and 'Z'. |
To generate a VCD file, perform the following steps:
Open your Simulink model, if it is not already open.
Identify where you want to add the To VCD File block. For example, you might temporarily replace a scope with this block.
In the Simulink Library Browser, click the EDA Simulator Link IN block library.
Copy the To VCD File block from the Library Browser to your model by clicking the block and dragging it from the browser to your model window.
Connect the block ports to appropriate blocks in your Simulink model.
Configure the To VCD File block by specifying values for parameters in the Block Parameters dialog box, as follows:
Double-click the block icon. Simulink displays the following dialog box.
Specify a file name for the generated VCD file in the VCD file name text box.
If you specify a file name only, Simulink places the file in your current MATLAB directory.
Specify a complete path name to place the generated file in a different location.
If you want the generated file to have a .vcd file type extension, you must specify it explicitly.
Specify an integer in the Number of input ports text box that indicates the number of block input ports on which signal data is to be collected. The block can handle up to 943 (830,584) signals, each of which maps to a unique symbol in the VCD file.
Click OK.
Choose a timing relationship between Simulink and the HDL simulator. The time scale options specify a correspondence between one second of Simulink time and some quantity of HDL simulator time. Choose relative time or absolute time. For more on the To VCD File time scale, see the reference documentation for the To VCD File block.
Run the simulation. Simulink captures the simulation data in the VCD file as the simulation runs.
For a description of the VCD file format see VCD File Format.
| Preparing for Cosimulation | Running Cosimulation Sessions | |
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