EDA Simulator Link™ IN

Coding an EDA Simulator Link IN MATLAB Application

Overview

The EDA Simulator Link IN software provides a means for verifying and visualizing Cadence Incisive HDL modules within the MATLAB environment. You do so by coding an HDL model and a MATLAB function that can share data with the HDL model. This chapter discusses the programming, interfacing, and scheduling conventions for MATLAB functions that communicate with the HDL simulator.

EDA Simulator Link IN software supports two types of MATLAB functions that interface to HDL modules:

• MATLAB test bench functions let you verify the performance of the HDL model, or of components within the model. A test bench function drives values onto signals connected to input ports of an HDL design under test and receives signal values from the output ports of the module.

  The syntax of a MATLAB test bench function is

  function [iport, tnext] = MyFunctionName(oport, tnow, portinfo)
  

• MATLAB component functions simulate the behavior of components in the HDL model. A stub module (providing port definitions only) in the HDL model passes its input signals to the MATLAB component function. The MATLAB component processes this data and returns the results to the outputs of the stub module. A MATLAB component typically provides some functionality (such as a filter) that is not yet implemented in the HDL code.

  The syntax of a MATLAB component function is

  function [oport, tnext] = MyFunctionName(iport, tnow, portinfo)
  

These two types of MATLAB functions are referred to collectively as MATLAB link functions, and a test bench or component session may be referred to as a MATLAB link session.

The programming, interfacing, and scheduling conventions for test bench functions and MATLAB component functions are almost identical. Most of this chapter focuses on test bench functions, but in general all operations can be performed on and with both link functions. The test bench section is followed by a discussion of MATLAB component functions and how to use them.

Refer to EDA Simulator Link IN Machine Configuration Requirements for valid machine configurations.

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Process for Coding an EDA Simulator Link IN MATLAB Application

This section provides an overview of the steps required to develop an HDL model for use with MATLAB and the EDA Simulator Link IN software. To program the HDL component of an EDA Simulator Link IN application,

1. Code the HDL model for MATLAB verification (see Coding HDL Modules for MATLAB Verification).

2. Compile the HDL model (see Compiling and Debugging the HDL Model).

3. Code the required MATLAB test bench or MATLAB component functions (see Coding MATLAB Link Functions).

4. Place the MATLAB functions on the MATLAB search path

The following figure shows how a MATLAB function wraps around and communicates with the HDL simulator during a test bench simulation session.

The following figure shows how an HDL simulator wraps around a MATLAB component function and how MATLAB communicates with the HDL simulator during a component simulation session.

When linked with MATLAB, the HDL simulator functions as the client, with MATLAB as the server. The following figure shows a multiple-client scenario connecting to the server at TCP/IP socket port 4449.

The MATLAB server can service multiple simultaneous HDL simulator sessions and HDL modules. However, you should follow recommended guidelines to ensure the server can track the I/O associated with each module and session. The MATLAB server, which you start with the supplied MATLAB function hdldaemon, waits for connection requests from instances of the HDL simulator running on the same or different computers. When the server receives a request, it executes the specified MATLAB function you have coded to perform tasks on behalf of a module in your HDL design. Parameters that you specify when you start the server indicate whether the server establishes shared memory or TCP/IP socket communication links.

Refer to EDA Simulator Link IN Machine Configuration Requirements for valid machine configurations.

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Coding HDL Modules for MATLAB Verification

• Overview

• Choosing an HDL Module Name

• Specifying Port Direction Modes

• Specifying Port Data Types

• Sample VHDL Entity Definition

• Compiling and Debugging the HDL Model

• Loading an HDL Design for Verification

Overview

The most basic element of communication in the EDA Simulator Link IN interface is the HDL module. The interface passes all data between the HDL simulator and MATLAB as port data. The EDA Simulator Link IN software works with any existing HDL module. However, when you code an HDL module that is targeted for MATLAB verification, you should consider its name, the types of data to be shared between the two environments, and the direction modes. The sections within this chapter cover these topics.

Choosing an HDL Module Name

Although not required, when naming the HDL module, consider choosing a name that also can be used as a MATLAB function name. (Generally, naming rules for VHDL or Verilog and MATLAB are compatible.) By default, EDA Simulator Link IN software assumes that an HDL module and its simulation function share the same name. See Naming a MATLAB Link Function.

For details on MATLAB function-naming guidelines, see "MATLAB Programming Tips" on files and file names in the MATLAB documentation.

Specifying Port Direction Modes

In your module statement, you must specify each port with a direction mode (input, output, or bidirectional). The following table defines these three modes

Specifying Port Data Types

This section describes how to specify data types compatible with MATLAB for ports in your HDL modules. For details on how the EDA Simulator Link IN interface converts data types for the MATLAB environment, see Performing Data Type Conversions.

Note   If you use unsupported types, the EDA Simulator Link IN software issues a warning and ignores the port at run time. For example, if you define your interface with five ports, one of which is a VHDL access port, at run time, then the interface displays a warning and your M-code sees only four ports.

Port Data Types for VHDL Entities.   In your entity statement, you must define each port that you plan to test with MATLAB with a VHDL data type that is supported by the EDA Simulator Link IN software. The interface can convert scalar and array data of the following VHDL types to comparable MATLAB types:

• STD_LOGIC, STD_ULOGIC, BIT, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR, and BIT_VECTOR

• INTEGER and NATURAL

• REAL

• TIME

• Enumerated types, including user-defined enumerated types and CHARACTER

The interface also supports all subtypes and arrays of the preceding types.

Note   The EDA Simulator Link IN software does not support VHDL extended identifiers for the following components: Port and signal names used in cosimulation Enum literals when used as array indices of port and signal names used in cosimulation However, the software does support basic identifiers for VHDL.

Port Data Types for Verilog Modules.   In your module definition, you must define each port that you plan to test with MATLAB with a Verilog port data type that is supported by the EDA Simulator Link IN software. The interface can convert data of the following Verilog port types to comparable MATLAB types:

• reg

• integer

• wire

Note   EDA Simulator Link IN software does not support Verilog escaped identifiers for port and signal names used in cosimulation. However, it does support simple identifiers for Verilog.

Sample VHDL Entity Definition

The next sample VHDL code fragment defines the entity decoder. By default, the entity is associated with MATLAB test bench function decoder.

The keyword PORT marks the start of the entity's port clause, which defines two IN ports—isum and qsum—and three OUT ports—adj, dvalid, and odata. The output ports drive signals to MATLAB function input ports for processing. The input ports receive signals from the MATLAB function output ports.

Both input ports are defined as vectors consisting of five standard logic values. The output port adj is also defined as a standard logic vector, but consists of only two values. The output ports dvalid and odata are defined as scalar standard logic ports. For information on how the EDA Simulator Link IN interface converts data of standard logic scalar and array types for use in the MATLAB environment, see Performing Data Type Conversions.

ENTITY decoder IS
PORT (
  isum   : IN std_logic_vector(4 DOWNTO 0);
  qsum   : IN std_logic_vector(4 DOWNTO 0);
  adj    : OUT std_logic_vector(1 DOWNTO 0);
  dvalid : OUT std_logic;
  odata  : OUT std_logic);
END decoder ;

Compiling and Debugging the HDL Model

After you create or edit your HDL source files, use the HDL simulator compiler to compile and debug the code.

The Cadence Incisive simulator allows for 1-step and 3-step processes for HDL compilation, elaboration, and simulation. The following Cadence Incisive simulator command compiles the Verilog file test.v:

sh> ncvlog test.v

The following Cadence Incisive simulator command compiles and elaborates the Verilog design test.v, and then loads it for simulation, in a single step:

sh> ncverilog +gui +access+rwc +linedebug test.v 

The following sequence of Cadence Incisive simulator commands performs all the same processes in multiple steps:

sh> ncvlog -linedebug test.v
sh> ncelab -access +rwc test
sh> ncsim test

Note   You should provide read/write access to the signals that are connecting to the MATLAB session for cosimulation. The previous example shows how to provide read/write access to all signals in your design. For higher performance, you want to provide access only to those signals used in cosimulation. See the description of the +access flag to ncverilog and the -access argument to ncelab for details.

For more examples, see the EDA Simulator Link IN tutorials. For details on using the Cadence Incisive compiler, see the simulator documentation.

Loading an HDL Design for Verification

After you start the HDL simulator from MATLAB with a call to nclaunch, load an instance of an HDL module for verification with the HDL simulator command hdlsimmatlab. At this point, it is assumed that you have coded and compiled your HDL model as explained in Coding HDL Modules for MATLAB Verification. Issue the HDL simulator command hdlsimmatlab for each instance of an entity or module in your model that you want to cosimulate. For example:

hdlsimmatlab work.osc_top

This command loads the EDA Simulator Link IN library, opens a simulation workspace for osc_top, and displays a series of messages in the HDL simulator command window as the simulator loads the entity (see demo for remaining code).

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Coding MATLAB Link Functions

• Process for Coding MATLAB Link Functions

• Defining Link Functions and Link Function Parameters

• Performing Data Type Conversions

• Sample MATLAB Test Bench Function

Process for Coding MATLAB Link Functions

Coding a MATLAB function that is to verify or visualize an HDL module or component, requires that you follow specific coding conventions. You must also understand the data type conversions that occur, and program data type conversions for operating on data and returning data to the HDL simulator.

To code a MATLAB link function that is to verify or visualize an HDL module or component, perform the following steps:

1. Learn the syntax for a MATLAB link function (see Defining Link Functions and Link Function Parameters).

2. Understand how EDA Simulator Link IN software converts HDL modules data for use in the MATLAB environment (see Performing Data Type Conversions).

3. Choose a name for the MATLAB function (see Choosing an HDL Module Name).

4. Define expected parameters in the function definition line (see Defining Link Functions and Link Function Parameters).

5. Determine the types of port data being passed into the function (see Defining Link Functions and Link Function Parameters).

6. Extract and, if appropriate for the simulation, apply information received in the portinfo structure (see Gaining Access to and Applying Port Information).

7. Convert data for manipulation in the MATLAB environment, as necessary (see Converting HDL Data to Send to MATLAB).

8. Convert data that needs to be returned to the HDL simulator (see Converting Data for Return to the HDL Simulator).

Defining Link Functions and Link Function Parameters

The syntax of a MATLAB component function is

function [oport, tnext] = MyFunctionName(iport, tnow, portinfo)

The syntax of a MATLAB test bench function is

function [iport, tnext] = MyFunctionName(oport, tnow, portinfo)

The input/output arguments (iport and oport) for a MATLAB component function are the reverse of the port arguments for a MATLAB test bench function. That is, the MATLAB component function returns signal data to the outputs and receives data from the inputs of the associated HDL module.

Initialize the function outputs to empty values at the beginning of the function as in the following example:

tnext = [];
oport = struct();

For more information on using tnext and tnow for simulation scheduling, see Scheduling Options for a Link Session.

The following table describes each of the link function parameters and the roles they play in each of the functions.

Note   When you import VHDL signals, signal names in iport, oport, and portinfo are returned in all capitals. You can use the port information to create a generic MATLAB function that operates differently depending on the port information supplied at startup. For more information on port data, see Gaining Access to and Applying Port Information.

Oscfilter Function Example.   The following code gives the definition of the oscfilter MATLAB component function.

function [oport,tnext] = oscfilter(iport, tnow, portinfo)

The function name oscfilter, differs from the entity name u_osc_filter. Therefore, the component function name must be passed in explicitly to the matlabcp command that connects the function to the associated HDL instance using the -mfunc parameter.

The function definition specifies all required input and output parameters, as listed here:

The following figure shows the relationship between the HDL entity's ports and the MATLAB function's iport and oport parameters.

Gaining Access to and Applying Port Information.   EDA Simulator Link IN software passes information about the entity or module under test in the portinfo structure. The portinfo structure is passed as the third argument to the function. It is passed only in the first call to your MATLAB function. You can use the information passed in the portinfo structure to validate the entity or module under simulation. Three fields supply the information, as indicated in the next sample. . The content of these fields depends on the type of ports defined for the VHDL entity or Verilog module.

portinfo.field1.field2.field3

The following table lists possible values for each field and identifies the port types for which the values apply.

HDL Port Information

The first call to the MATLAB function has three arguments including the portinfo structure. Checking the number of arguments is one way that you can ensure that portinfo was passed. For example:

if(nargin ==3)
 tscale  = portinfo.tscale;
end

Performing Data Type Conversions

To successfully use the EDA Simulator Link IN software with the HDL simulator and MATLAB or Simulink, you need to understand the data type conversions that the EDA Simulator Link IN software performs to transmit and receive data between HDL modules and the MATLAB environment.

Converting HDL Data to Send to MATLAB.   If your HDL application needs to send HDL data to a MATLAB function, you may first need to convert the data to a type supported by MATLAB and the EDA Simulator Link IN software.

To program a MATLAB function for an HDL model, you must understand the type conversions required by your application. You may also need to handle differences between the array indexing conventions used by the HDL you are using and MATLAB (see following section).

The data types of arguments passed in to the function determine the following:

• The types of conversions required before data is manipulated

• The types of conversions required to return data to the HDL simulator

The following table summarizes how the EDA Simulator Link IN software converts supported VHDL data types to MATLAB types based on whether the type is scalar or array.

VHDL-to-MATLAB Data Type Conversions

The following table summarizes how the EDA Simulator Link IN software converts supported Verilog data types to MATLAB types. The software supports only scalar data types for Verilog.

Verilog-to-MATLAB Data Type Conversions

Array Indexing Differences Between MATLAB and HDL.   In multidimensional arrays, the same underlying OS memory buffer maps to different elements in MATLAB and the HDL simulator (this mapping only reflects different ways the different languages offer for naming the elements of the same array). When you use both matlabtb and matlabcp functions, be careful to assign and interpret values consistently in both applications.

In HDL, a multidimensional array declared as:

type matrix_2x3x4 is array (0 to 1, 4 downto 2) of std_logic_vector(8 downto 5);

has a memory layout as follows:

bit   01 02 03 04  05 06 07 08  09 10 11 12  13 14 15 16  17 18 19 20  21 22 23 24
 -
 dim1 0  0  0  0   0  0  0  0   0  0  0  0   1  1  1  1   1  1  1  1   1  1  1  1
 dim2 4  4  4  4   3  3  3  3   2  2  2  2   4  4  4  4   3  3  3  3   2  2  2  2
 dim3 8  7  6  5   8  7  6  5   8  7  6  5   8  7  6  5   8  7  6  5   8  7  6  5

This same layout corresponds to the following MATLAB 4x3x2 matrix:

 bit  01 02 03 04  05 06 07 08  09 10 11 12  13 14 15 16  17 18 19 20  21 22 23 24
 -
 dim1 1  2  3  4   1  2  3  4   1  2  3  4   1  2  3  4   1  2  3  4   1  2  3  4 
 dim2 1  1  1  1   2  2  2  2   3  3  3  3   1  1  1  1   2  2  2  2   3  3  3  3 
 dim3 1  1  1  1   1  1  1  1   1  1  1  1   2  2  2  2   2  2  2  2   2  2  2  2

Therefore, if H is the HDL array and M is the MATLAB matrix, the following indexed values are the same:

 b1  H(0,4,8) = M(1,1,1)
 b2  H(0,4,7) = M(2,1,1)
 b3  H(0,4,6) = M(3,1,1)
 b4  H(0,4,5) = M(4,1,1)
 b5  H(0,3,8) = M(1,2,1)
 b6  H(0,3,7) = M(2,2,1)
 ...
 b19 H(1,3,6) = M(3,2,2)
 b20 H(1,3,5) = M(4,2,2)
 b21 H(1,2,8) = M(1,3,2)
 b22 H(1,2,7) = M(2,3,2)
 b23 H(1,2,6) = M(3,3,2)
 b24 H(1,2,5) = M(4,3,2)

You can extend this indexing to N-dimensions. In general, the dimensions—if numbered from left to right—are reversed. The right-most dimension in HDL corresponds to the left-most dimension in MATLAB.

Converting Data for Manipulation.   Depending on how your simulation MATLAB function uses the data it receives from the HDL simulator, you may need to code the function to convert data to a different type before manipulating it. The following table lists circumstances under which you would require such conversions.

Required Data Conversions

datas(inc+1) = double(idata);

uval = mvl2dec(oport.val')

suval = mvl2dec(oport.val'), true);

The following code excerpt illustrates data type conversion of data passed in to a callback:

InDelayLine(1) = InputScale * mvl2dec(iport.osc_in',true);

This example tests port values of VHDL type STD_LOGIC and STD_LOGIC_VECTOR by using the all function as follows:

all(oport.val == '1' | oport.val 
== '0')

This example returns True if all elements are '1' or '0'.

Converting Data for Return to the HDL Simulator.   If your simulation MATLAB function needs to return data to the HDL simulator, you may first need to convert the data to a type supported by the EDA Simulator Link IN software. The following tables list circumstances under which such conversions are required for VHDL and Verilog.

Note   When data values are returned to the HDL simulator, the char array size must match the HDL type, including leading zeroes, if needed. For example: oport.signal = dec2mvl(2) will only work if signal is a 2-bit type in HDL. If the HDL type is anything else, you must specify the second argument: oport.signal = dec2mvl(2, N) where N is the number of bits in the HDL data type.

VHDL Conversions for the HDL Simulator

iport.s1 = 'X'; %STD_LOGIC
iport.bit = '1'; %BIT

iport.s1v = 'X10ZZ'; %STD_LOGIC_VECTOR
iport.bitv = '10100'; %BIT_VECTOR
iport.uns = dec2mvl(10,8); %UNSIGNED, 8 bits

iport.int = int32(1:10)';

iport.dbl = ones(2,2); 

iport.t1 = int64(1:10)'; %Simulator time
                         %increments
iport.t2 = 1e-9; %1 nsec

iport.char = {'''A''', '''B'''}; %Character
                                 %literal
iport.udef = 'mylabel'; %User-defined label

oport.slva =dec2mvl([23 99],8)';

Verilog Conversions for the HDL Simulator

iport.bit = '1'; 

Sample MATLAB Test Bench Function

This section uses a sample MATLAB function to identify sections of a MATLAB test bench function required by the EDA Simulator Link IN software. You can see the full text of the code used in this sample in the section M-Function Example: manchester_decoder.m.

As the first step to coding a MATLAB test bench function, you must understand how the data modeled in the VHDL entity maps to data in the MATLAB environment. The VHDL entity decoder is defined as follows:

ENTITY decoder IS
PORT (
  isum   : IN std_logic_vector(4 DOWNTO 0);
  qsum   : IN std_logic_vector(4 DOWNTO 0); 
  adj    : OUT std_logic_vector(1 DOWNTO 0);
  dvalid : OUT std_logic;
  odata  : OUT std_logic
  );
END decoder ;

The following discussion highlights key lines of code in the definition of the manchester_decoder MATLAB function:

1. Specify the MATLAB function name and required parameters.

   The following code is the function declaration of the manchester_decoder MATLAB function.

   function [iport,tnext] = manchester_decoder(oport,tnow,portinfo)
   

   See Defining Link Functions and Link Function Parameters.

   The function declaration performs the following actions:

   • Names the function. This declaration names the function manchester_decoder, which differs from the entity name decoder. Because the names differ, the function name must be specified explicitly later when the entity is initialized for verification with the matlabtb or matlabtbeval HDL simulator command. See Naming a MATLAB Link Function.

   • Defines required argument and return parameters. A MATLAB test bench function must return two parameters, iport and tnext, and pass three arguments, oport, tnow, and portinfo, and must appear in the order shown. See Defining Link Functions and Link Function Parameters.

     The function outputs must be initialized to empty values, as in the following code example:

     tnext = [];
     iport = struct();
     

     You should initialize the function outputs at the beginning of the function, to follow recommended best practice.

     The following figure shows the relationship between the entity's ports and the MATLAB function's iport and oport parameters.

     

     For more information on the required MATLAB link function parameters, see Defining Link Functions and Link Function Parameters.

2. Make note of the data types of ports defined for the entity being simulated.

   The EDA Simulator Link IN software converts HDL data types to comparable MATLAB data types and vice versa. As you develop your MATLAB function, you must know the types of the data that it receives from the HDL simulator and needs to return to the HDL simulator.

   The VHDL entity defined for this example consists of the following ports

   VHDL Example Port Definitions

   Port	Direction	Type...	Converts to/Requires Conversion to...
   isum	IN	STD_LOGIC_VECTOR(4 DOWNTO 0)	A 5-bit column or row vector of characters where each bit maps to standard logic character 0 or 1.
   qsum	IN	STD_LOGIC_VECTOR(4 DOWNTO 0)	A 5-bit column or row vector of characters where each bit maps to standard logic character 0 or 1.
   adj	OUT	STD_LOGIC_VECTOR(1 DOWNTO 0)	A 2-element column vector of characters. Each character matches a corresponding character literal that represents a logic state and maps to a single bit.
   dvalid	OUT	STD_LOGIC	A character that matches the character literal representing the logic state.
   odata	OUT	STD_LOGIC	A character that matches the character literal representing the logic state.

   For more information on interface data type conversions, see Performing Data Type Conversions.

3. Set up any required timing parameters.

   The tnext assignment statement sets up timing parameter tnext such that the simulator calls back the MATLAB function every nanosecond.

   tnext = tnow+1e-9;

4. Convert output port data to appropriate MATLAB data types for processing.

   The following code excerpt illustrates data type conversion of output port data.

   %% Compute one row and plot
   isum = isum + 1;
   adj(isum) = mvl2dec(oport.adj');
   data(isum) = mvl2dec([oport.dvalid oport.odata]);
   .
   .
   .
   

   The two calls to mvl2dec convert the binary data that the MATLAB function receives from the entity's output ports, adj, dvalid, and odata to unsigned decimal values that MATLAB can compute. The function converts the 2-bit transposed vector oport.adj to a decimal value in the range 0 to 4 and oport.dvalid and oport.odata to the decimal value 0 or 1.

   Performing Data Type Conversions provides a summary of the types of data conversions to consider when coding simulation MATLAB functions.

5. Convert data to be returned to the HDL simulator.

   The following code excerpt illustrates data type conversion of data to be returned to the HDL simulator.

    if isum == 17
      iport.isum = dec2mvl(isum,5);
      iport.qsum = dec2mvl(qsum,5);    
   else
      iport.isum = dec2mvl(isum,5);
   end
   

   The three calls to dec2mvl convert the decimal values computed by MATLAB to binary data that the MATLAB function can deposit to the entity's input ports, isum and qsum. In each case, the function converts a decimal value to 5-element bit vector with each bit representing a character that maps to a character literal representing a logic state.

   Converting Data for Return to the HDL Simulator provides a summary of the types of data conversions to consider when returning data to the HDL simulator.

M-Function Example: manchester_decoder.m

function [iport,tnext] = manchester_decoder(oport,tnow,portinfo)
% MANCHESTER_DECODER  Test bench for VHDL 'decoder'
%  [IPORT,TNEXT]=MANCHESTER_DECODER(OPORT,TNOW,PORTINFO) -
%    Implements a test of the VHDL decoder entity which is part
%    of the Manchester receiver demo.  This test bench plots
%    the IQ mapping produced by the decoder.
%
%      iport              oport
%            +-----------+
% isum -(5)->|           |-(2)-> adj
% qsum -(5)->| decoder   |-(1)-> dvalid
%            |           |-(1)-> odata
%            +-----------+
%
%   isum - Inphase Convolution value
%   qsum - Quadrature Convolution value
%   adj  - Clock adjustment ('01','00','10')
%   dvalid - Data validity ('1' = data is valid)
%   odata - Recovered data stream
%
% Adjust = 0 (00b), generate full 16 cycle waveform

%   Copyright 2003-2004 The MathWorks, Inc.
%   $Revision: 1.1.4.1 $  $Date$

persistent isum;
persistent qsum;
%persistent ga;
persistent x;
persistent y;
persistent adj;
persistent data;
global testisdone;
% This useful feature allows you to manually
% reset the plot by simply typing: >manchester_decoder
tnext = [];
iport = struct();

if nargin == 0,
    isum = [];
    return;
end

if exist('portinfo') == 1
    isum = [];
end

tnext = tnow+1e-9;
if isempty(isum),  %% First call
    scale = 9;
    isum = 0;
    qsum = 0;
    for k=1:2,
        ga(k) = subplot(2,1,k);
        axis([-1 17 -1 17]);
        ylabel('Quadrature');
        line([0 16],[8 8],'Color','r','LineStyle',':','LineWidth',1)
        line([8 8],[0 16],'Color','r','LineStyle',':','LineWidth',1)
    end
    xlabel('Inphase');
    subplot(2,1,1);
    title('Clock Adjustment (adj)');
    subplot(2,1,2);
    title('Data with Validity');
    iport.isum = '00000';
    iport.qsum = '00000';
    return;
end

% compute one row, then plot
isum = isum + 1;
adj(isum) = bin2dec(oport.adj');
data(isum) = bin2dec([oport.dvalid oport.odata]);

if isum == 17,
    subplot(2,1,1);
    for k=0:16,
        if adj(k+1) == 0,  % Bang on!
            line(k,qsum,'color','k','Marker','o');
        elseif adj(k+1) == 1,  %
            line(k,qsum,'color','r','Marker','<');
        else
            line(k,qsum,'color','b','Marker','>');
        end
    end
    subplot(2,1,2);
    for k=0:16,
        if data(k+1) < 2,  % Invalid
            line(k,qsum,'color','r','Marker','X');
        else
            if data(k+1) == 2,  %Valid and 0!
                line(k,qsum,'color','g','Marker','o');
            else
                line(k,qsum,'color','k','Marker','.');
            end
        end
    end

    isum = 0;
    qsum = qsum + 1;
    if qsum == 17,
        qsum = 0;
        disp('done');
        tnext = [];  % suspend callbacks
        testisdone = 1;
        return;
    end
    iport.isum = dec2bin(isum,5);
    iport.qsum = dec2bin(qsum,5);
else
    iport.isum = dec2bin(isum,5);
end

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MATLAB-Cadence Incisive Workflow

Associating a MATLAB Link Function with an HDL Module