| EDA Simulator Link™ IN | |
Cosimulate hardware component by communicating with HDL module instance executing in HDL simulator
EDA Simulator Link IN
The HDL Cosimulation block cosimulates a hardware component by applying input signals to and reading output signals from an HDL model under simulation in the HDL simulator. You can use this block to model a source or sink device by configuring the block with input or output ports only.
The tabbed panes on the block's dialog box let you configure:
Block input and output ports that correspond to signals (including internal signals) of an HDL module. You must specify a sample time for each output port; you can also specify a data type for each output port.
Type of communication and communication settings used to exchange data between simulators.
The timing relationship between units of simulation time in Simulink and the HDL simulator.
Rising-edge or falling-edge clocks to apply to your model. You can specify the period for each clock signal.
Tcl commands to run before and after the simulation.
The Ports pane provides fields for mapping signals of your HDL design to input and output ports in your block. The signals can be at any level of the HDL design hierarchy.
The Timescales pane lets you choose an optimal timing relationship between Simulink and the HDL simulator. You can configure either a relative timing relationship (Simulink seconds correspond to an HDL simulator-defined tick interval) or an absolute timing relationship (Simulink seconds correspond to an absolute unit of HDL simulator time).
The Connection pane specifies the communications mode used between Simulink and the HDL simulator. If you use TCP socket communication, this pane provides fields for specifying a socket port and for the host name of a remote computer running the HDL simulator. The Connection pane also provides the option for bypassing the cosimulation block during Simulink simulation.
The Clocks pane lets you create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model.
The Tcl pane provides a way of specifying tools command language (Tcl) commands to be executed before and after the HDL simulator simulates the HDL component of your Simulink model. The Pre-simulation commands field on this pane is particularly useful for simulation initialization and startup operations, but it cannot be used to change simulation state.
Note You must make sure that signals being used in cosimulation have read/write access (this is done through the HDL simulator—see product documentation for details). This rule applies to all signals on the Ports, Clocks, and Tcl panes. |
The Block Parameters dialog box consists of the following tabbed panes of configuration options:
Specify fields for mapping signals of your HDL design to input and output ports in your block. Simulink deposits an input port signal on an HDL simulator signal at the signal's sample rate. Conversely, Simulink reads an output port signal from a specified HDL simulator signal at the specified sample rate.
In general, Simulink handles port sample periods as follows:
If an input port is connected to a signal that has an explicit sample period, based on forward propagation, Simulink applies that rate to the port.
If an input port is connected to a signal that does not have an explicit sample period, Simulink assigns a sample period that is equal to the least common multiple (LCM) of all identified input port sample periods for the model.
After Simulink sets the input port sample periods, it applies user-specified output sample times to all output ports. An explicit sample time must be specified for each output port.
In addition to specifying output port sample times, you can force the fixed point data types on output ports. For example, setting the Data Type property of an 8-bit output port to Signed and setting its Fraction Length property to 5 would force the data type to sfix8_En5.
(Note, however, that can not force width; the width is always inherited from the HDL simulator. )
Note The Data Type and Fraction Length properties apply only to the following signals:
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Input/output ports can be set here as well; specify port as both input and output.
The list at the center of the pane displays HDL signals corresponding to ports on the HDL Cosimulation block.
Maintain this list with the buttons on the left of the pane:
Auto Fill — Transmit a port information request to the HDL simulator. The port information request returns port names and information from an HDL model (or module) under simulation in the HDL simulator, and automatically enters this information into the ports list. See Obtaining Signal Information Automatically from the HDL Simulator for a detailed description of this feature.
New — Add a new signal to the list and select it for editing.
Delete — Remove a signal from the list.
Up — Move the selected signal up one position in the list.
Down — Move the selected signal down one position in the list.
To commit edits to the Simulink model, you must also click Apply.
Note When importing VHDL signals, signal names are returned in all capitals. |
To edit the a signal name, double-click on the name. Set the signal properties on the same line and in the appropriate columns. The properties of a signal are as follows.
Specifies the signal path name, using the HDL simulator path name syntax. For example, a path name for an input port might be manchester.samp. The signal can be at any level of the HDL design hierarchy. The HDL Cosimulation block port corresponding to the signal is labeled with the Full HDL Name.
For rules on specifying signal/port and module path specifications in Simulink, see Specifying HDL Signal/Port and Module Paths for Cosimulation.
Note You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field, using the standard copy and paste commands in the HDL simulator and Simulink (as long as you use the ‘Path.Name' view and not ‘Db::Path.Name' view). After pasting a signal path name into the Full HDL Name field, you must click the Apply button to complete the paste operation and update the signal list. |
Select either Input, Output, or both.
Input designates signals of your HDL module that are to be driven by Simulink. Simulink deposits values on the specified the HDL simulator signal at the signal's sample rate.
Note When you define a block input port, make sure that only one source is set up to drive input to that signal. For example, you should avoid defining an input port that has multiple instances. If multiple sources drive input to a single signal, your simulation model may produce unexpected results. |
Output designates signals of your HDL module that are to be read by Simulink. For output signals, you must specify an explicit sample time. You can also specify a data type (except width), if desired (see Date Type and Fraction Length in a following section).
Since Simulink signals do not have the semantic of tri-states (there is no 'Z' value), it is not meaningful to connect to a bi-directional HDL signal directly. In order to interface with bi-directional signals, you can interface to the input of the output driver, the enable of the output driver, and the output of the input driver. This leaves the actual tri-state buffer in HDL where resolution functions can handle interfacing with other tri-state buffers.
This property is enabled only for output signals. You must specify an explicit sample time.
Sample Time represents the time interval between consecutive samples applied to the output port. The default sample time is 1. The exact interpretation of the output port sample time depends on the settings of the Timescales pane of the HDL Cosimulation block (see Timescales Pane). See also Representation of Simulation Time.
These two related parameters apply only to output signals.
The Data Type property is enabled only for output signals. You can direct Simulink to determine the data type, or you can assign an explicit data type (with option fraction length). By explicitly assigning a data type, you can force fixed point data types on output ports of an HDL Cosimulation block.
The Fraction Length property specifies the size, in bits, of the fractional part of the signal in fixed-point representation. Fraction Length is enabled when the Data Type property is not set to Inherit.
Output port data types are determined by the signal width and by the Data Type and Fraction Length properties of the signal.
Note The Data Type and Fraction Length properties apply only to the following signals:
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To assign a port data type, set the Data Type and Fraction Length properties as follows:
Select Inherit from the Data Type list if you want Simulink to determine the data type.
Inherit is the default setting. When Inherit is selected, the Fraction Length edit field is disabled.
Simulink always double checks that the word-length back propagated by Simulink matches the word length queried from the HDL simulator. If they don't match an error is generated. For example, if a Signal Specification block is connected to an output, Simulink will force the data type specified by Signal Specification block on the output port.
If Simulink cannot determine the data type of the signal connected to the output port, it will query the HDL simulator for the data type of the port. As an example, if the HDL simulator returns the VHDL data type STD_LOGIC_VECTOR for a signal of size N bits, the data type ufixN is forced on the output port. (The implicit fraction length is 0.)
Select Signed from the Data Type list if you want to explicitly assign a signed fixed point data type. When Signed is selected, the Fraction Length edit field is enabled. The port is assigned a fixed point type sfixN_EnF, where N is the signal width and F is the Fraction Length.
For example, if you specify Data Type as Signed and a Fraction Length of 5 for a 16-bit signal, Simulink forces the data type to sfix16_En5. For the same signal with a Data Type set to Signed and Fraction Length of -5, Simulink forces the data type to sfix16_E5.
Select Unsigned from the Data Type list if you want to explicitly assign an unsigned fixed point data type When Unsigned is selected, the Fraction Length edit field is enabled. The port is assigned a fixed point type ufixN_EnF, where N is the signal width and F is the Fraction Length.
For example, if you specify Data Type as Unsigned and a Fraction Length of 5 for a 16-bit signal, Simulink forces the data type to ufix16_En5. For the same signal with a Data Type set to Unsigned and Fraction Length of -5 , Simulink forces the data type to ufix16_E5.
This figure shows the default configuration of the Connection pane. By default, the block is configured for shared memory communication between Simulink and the HDL simulator, running on a single computer.
If you select TCP/IP socket mode communication, the pane displays additional properties, as shown in the following figure.
If you want to bypass the HDL simulator when running a Simulink simulation, use these options to specify what type of simulation connection you want. Select one of the following:
Full Simulation: Confirm interface and run HDL simulation (default).
Confirm Interface Only: Connect to the HDL simulator and check for proper signal names, dimensions, and data types, but do not run HDL simulation.
No Connection: Do not communicate with the HDL simulator. The HDL simulator does not need to be started.
With the 2nd and 3rd options, the EDA Simulator Link™ IN cosimulation interface does not communicate with the HDL simulator during Simulink simulation.
Select this option if you want to run Simulink and the HDL simulator on the same computer. When both applications run on the same computer, you have the choice of using shared memory or TCP sockets for the communication channel between the two applications. If this option is deselected, only TCP/IP socket mode is available, and the Connection method list is disabled.
This list is enabled when The HDL Simulator is running on this computer is selected. Select Socket if you want Simulink and the HDL simulator to communicate via a designated TCP/IP socket. Select Shared memory if you want Simulink and the HDL simulator to communicate via shared memory. For more information on these connection methods, see Communicating with MATLAB or Simulink and the HDL Simulator.
If Simulink and the HDL simulator are running on different computers, this text field is enabled. The field specifies the host name of the computer that is running your HDL simulation in the HDL simulator.
Indicate a valid TCP socket port number or service for your computer system (if not using shared memory). For information on choosing TCP socket ports, see Choosing TCP/IP Socket Ports.
When this option is selected, Simulink indicates information about the selected communication method and (if applicable) communication options information on the HDL Cosimulation block icon. If shared memory is selected, the icon displays the string SharedMem. If TCP socket communication is selected, the icon displays the host name and port number in the format hostname:port.
In a model that has multiple HDL Cosimulation blocks, with each communicating to different instances of the HDL simulator in different modes, this information helps to distinguish between different cosimulation sessions.
The Timescales pane of the HDL Cosimulation block parameters dialog lets you choose a timing relationship between Simulink and the HDL simulator. The following figure shows the default settings of the Timescales pane.
The Timescales pane specifies a correspondence between one second of Simulink time and some quantity of HDL simulator time. This quantity of HDL simulator time can be expressed in one of the following ways:
In relative terms (i.e., as some number of HDL simulator ticks). In this case, the cosimulation is said to operate in relative timing mode. Relative timing mode is the default.
To use relative mode, select Tick from the list on the right, and enter the desired number of ticks in the edit box. For example, in the figure below the Timescales pane is configured for a relative timing correspondence of 10 HDL simulator ticks to 1 Simulink second.
In absolute units (such as milliseconds or nanoseconds). In this case, the cosimulation is said to operate in absolute timing mode.
To use absolute mode, select a unit of absolute time (available units are fs, ps, ns, us, ms, s ) from the list on the right. Then enter a scale factor in the left-side edit box. For example, in the figure below the Timescales pane is configured for an absolute timing correspondence of 1 HDL simulator second to 1 Simulink second.
For more information on calculating relative and absolute timing modes, see Defining the Simulink and HDL Simulator Timing Relationship.
For detailed information on the relationship between Simulink and the HDL simulator during cosimulation, and on the operation of relative and absolute timing modes, see Representation of Simulation Time.
Create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model using the Clocks pane of the HDL Cosimulation block. You can either specify an explicit period for each clock, or accept a default period of 2. Simulink attempts to create a clock that has a 50% duty cycle and a predefined phase that is inverted for the falling edge case.
Whether you have configured the Timescales pane for relative timing mode or absolute timing mode, the following restrictions apply to clock periods:
If you specify an explicit clock period, you must enter a sample time equal to or greater than 2 resolution units (ticks).
If the clock period (whether explicitly specified or defaulted) is not an even integer, Simulink cannot create a 50% duty cycle, and therefore the EDA Simulator Link IN software creates the falling edge at
(rounded down to the nearest integer).
The following figure shows a timing diagram that includes rising-edge and falling-edge clocks with a Simulink sample period of T=10 and an HDL simulator resolution limit of 1 ns. The figure also shows that given those timing parameters, the clock duty cycle is 50%.
For more information on calculating relative and absolute timing modes, see Defining the Simulink and HDL Simulator Timing Relationship .
The scrolling list at the center of the pane displays HDL clocks that drive values to the HDL signals that you are modeling, using the deposit method.
Maintain the list of clock signals with the buttons on the left of the pane:
New — Add a new clock signal to the list and select it for editing.
Delete — Remove a clock signal from the list.
Up — Move the selected clock signal up one position in the list.
Down — Move the selected clock signal down one position in the list.
To commit edits to the Simulink model, you must also click Apply.
To edit the name of a clock signal, double-click it and enter the correct name. To edit the properties of a clock signal, select the appropriate property in that signal row. The properties of a clock signal are
Specify each clock as a signal path name, using the HDL simulator path name syntax. A sample path name for a clock might be manchester.clk.
For information about and requirements for path specifications in Simulink, see Specifying HDL Signal/Port and Module Paths for Cosimulation.
Note You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field, using the standard copy and paste commands in the HDL simulator and Simulink (as long as you use the ‘Path.Name' view and not ‘Db::Path.Name' view). After pasting a signal path name into the Full HDL Name field, you must click the Apply button to complete the paste operation and update the signal list. |
Select Rising or Falling to specify either a rising-edge clock or a falling-edge clock.
You must either specify the clock period explicitly, or accept the default period of 2.
If you specify an explicit clock period, you must enter a sample time equal to or greater than 2 resolution units (ticks).
If the clock period (whether explicitly specified or defaulted) is not an even integer, Simulink cannot create a 50% duty cycle, and therefore the EDA Simulator Link IN software creates the falling edge at
(rounded down to the nearest integer).
Note Vectored signals in the Clocks pane are not supported. Signals must be logic types with '1' and '0' values. |
Specify tools command language (Tcl) commands to be executed before and after the HDL simulator simulates the HDL component of your Simulink model
Contains Tcl commands to be executed before the HDL simulator simulates the HDL component of your Simulink model. You can specify one Tcl command per line in the text box, or enter multiple commands per line by appending each command with a semicolon (;), the standard Tcl concatenation operator.
Alternatively, you can create an HDL simulator Tcl script that lists Tcl commands and then specify that file with the HDL simulator source command as follows:
source mycosimstartup.script_extension
Use of this field can range from something as simple as a one-line echo command to confirm that a simulation is running to a complex script that performs an extensive simulation initialization and startup sequence.
Note The command string or Tcl script that you specify for this parameter cannot include commands that load an HDL simulator project or modify simulator state. For example, they cannot include commands such as run, stop, or reset. |
Contains Tcl commands to be executed after the HDL simulator simulates the HDL component of your Simulink model. You can specify one Tcl command per line in the text box or enter multiple commands per line by appending each command with a semicolon (;), the standard Tcl concatenation operator.
Alternatively, you can create an HDL simulator Tcl script that lists Tcl commands and then specify that file with the HDL simulator source command as follows:
source mycosimcleanup.script_extension
Notes
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