| Version 2.0 (R2007a) Link for Cadence Incisive Release Notes | ![]() |
This table summarizes what's new in V2.0 (R2007a):
| New Features and Changes | Version Compatibility Considerations | Fixed Bugs and Known Problems | Related Documentation at Web Site |
|---|---|---|---|
| Yes Details below | No | Bug Reports | No |
New features and changes introduced in this version are
Mixed-language (VHDL and Verilog) Cosimulation Support in Simulink Models
Option to Deactivate HDL Cosimulation for Faster Simulink Model Debugging
Link for Cadence® Incisive® now supports VHDL models directly. All Link for Cadence Incisive MATLAB functions, and the HDL Cosimulation block, offer the same language-transparent feature set for both Verilog and VHDL models. For more information, see Hardware Description Language (HDL) Support.
Link for Cadence Incisive software now supports mixed-language HDL models (models with both Verilog and VHDL components), allowing you to cosimulate VHDL and Verilog signals simultaneously.
This feature has the following limitation: The Cadence VHPI reports the incorrect simulator precision when simulating mixed Verilog/VHDL design. For more information, see Hardware Description Language (HDL) Support.
New option panel on the Connection Pane provides the following check boxes for bypassing the HDL simulator when running a Simulink simulation.

Select one of the following:
Full Simulation: Confirm interface and run HDL simulation (default).
Confirm Interface Only: Check HDL simulator for proper signal names, dimensions, and data types, but do not run HDL simulation.
No Connection: Do not communicate with the HDL simulator. The HDL simulator does not need to be started.
With the 2nd and 3rd options, the Link for Cadence Incisive interface does not communicate with the HDL simulator during Simulink simulation.
More about the HDL Cosimulation block can be found in HDL Cosimulation.
![]() | Version 2.1 (R2007b) Link for Cadence Incisive | Version 1.0 (R2006b+) Link for Cadence Incisive | ![]() |
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