Version 2.0 (R2007a) Link for Cadence Incisive

This table summarizes what's new in V2.0 (R2007a):

New Features and ChangesVersion Compatibility ConsiderationsFixed Bugs and Known ProblemsRelated Documentation at Web Site
Yes
Details below
NoBug ReportsNo

New features and changes introduced in this version are

Native VHDL Support

Link for Cadence® Incisive® now supports VHDL models directly. All Link for Cadence Incisive MATLAB functions, and the HDL Cosimulation block, offer the same language-transparent feature set for both Verilog and VHDL models. For more information, see Hardware Description Language (HDL) Support.

Mixed-language (VHDL and Verilog) Cosimulation Support in Simulink Models

Link for Cadence Incisive software now supports mixed-language HDL models (models with both Verilog and VHDL components), allowing you to cosimulate VHDL and Verilog signals simultaneously.

This feature has the following limitation: The Cadence VHPI reports the incorrect simulator precision when simulating mixed Verilog/VHDL design. For more information, see Hardware Description Language (HDL) Support.

Option to Deactivate HDL Cosimulation for Faster Simulink Model Debugging

New option panel on the Connection Pane provides the following check boxes for bypassing the HDL simulator when running a Simulink simulation.

Select one of the following:

With the 2nd and 3rd options, the Link for Cadence Incisive interface does not communicate with the HDL simulator during Simulink simulation.

More about the HDL Cosimulation block can be found in HDL Cosimulation.

  


 © 1984-2008- The MathWorks, Inc.    -   Site Help   -   Patents   -   Trademarks   -   Privacy Policy   -   Preventing Piracy   -   RSS