EDA Simulator Link™ MQ

Product Overview

Integration with Other Products

The EDA Simulator Link™ MQ cosimulation interface integrates MathWorks™ tools into the Electronic Design Automation (EDA) workflow. This integration enhances capabilities for field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) development. The software provides a bidirectional link between the Mentor Graphics hardware description language (HDL) simulator, ModelSim™, and The MathWorks™ MATLAB^® and Simulink^® products. Such linking makes direct hardware design verification and cosimulation possible. The integration of these tools allows users to apply each product to the tasks it does best:

• ModelSim — Hardware modeling in HDL and simulation

• MATLAB — Numerical computing, algorithm development, and visualization

• Simulink — Simulation of system-level designs and complex models

Note   ModelSim software may also be referred to as the HDL simulator throughout this document.

The EDA Simulator Link MQ software consists of MATLAB functions and HDL simulator commands that establish communication links between the HDL simulator and The MathWorks products. In addition, the link software contains a library of Simulink blocks that you may use to include HDL simulator designs in Simulink models for cosimulation.

EDA Simulator Link MQ software streamlines FPGA and ASIC development by integrating tools available for these processes:

1. Developing specifications for hardware design reference models

2. Implementing a hardware design in HDL based on a reference model

3. Verifying the design against the reference design

The following figure shows how the HDL simulator and MathWorks products fit into this hardware design scenario.

As the figure shows, EDA Simulator Link MQ software connects tools that traditionally have been used discretely to perform specific steps in the design process. By connecting these tools, the link simplifies verification by allowing you to cosimulate the implementation and original specification directly. This cosimulation results in significant time savings and the elimination of errors inherent to manual comparison and inspection.

In addition to the preceding design scenario, EDA Simulator Link MQ software enables you to work with tools in the following ways:

• Use MATLAB or Simulink to create test signals and software test benches for HDL code

• Use MATLAB or Simulink to provide a behavioral model for an HDL simulation

• Use MATLAB analysis and visualization capabilities for real-time insight into an HDL implementation

• Use Simulink to translate legacy HDL descriptions into system-level views

Note   You can cosimulate a module using SystemVerilog, SystemC or both with MATLAB or Simulink using the EDA Simulator Link MQ software. Write simple wrappers around the SystemC and make sure that the SystemVerilog cosimulation connections are to ports or signals of data types supported by the link cosimulation interface.

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Hardware Description Language (HDL) Support

All EDA Simulator Link MQ MATLAB functions and the HDL Cosimulation block offer the same language-transparent feature set for both Verilog and VHDL models.

EDA Simulator Link MQ software also supports mixed-language HDL models (models with both Verilog and VHDL components), allowing you to cosimulate VHDL and Verilog signals simultaneously. Both MATLAB and Simulink software can access components in different languages at any level.

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Linking with MATLAB and the HDL Simulator

When linked with MATLAB, the HDL simulator functions as the client, as the following figure shows.

In this scenario, a MATLAB server function waits for service requests that it receives from an HDL simulator session. After receiving a request, the server establishes a communication link and invokes a specified MATLAB function that computes data for, verifies, or visualizes the HDL module (coded in VHDL or Verilog) that is under simulation in the HDL simulator.

After the server is running, you can start and configure the HDL simulator or use with MATLAB with the supplied EDA Simulator Link MQ function vsim. Required and optional parameters allow you to specify the following:

• Tcl commands that execute as part of startup

• A specific ModelSim executable to start

• The name of a ModelSim DO file to store the complete startup script for future use or reference

The following figure shows how a MATLAB test bench function wraps around and communicates with the HDL simulator during a test bench simulation session.

The following figure shows how a MATLAB component function is wrapped around by and communicates with the HDL simulator during a component simulation session.

During the configuration process, EDA Simulator Link MQ software equips the HDL simulator with a set of customized command extensions you use to perform the following tasks:

• Load the HDL simulator with an instance of an HDL module to be tested with MATLAB

• Begin a MATLAB test bench or component session for that instance

When you begin a specific test bench session, you specify parameters that identify the following information:

• The mode and, if appropriate, TCP/IP data necessary for connecting to a MATLAB server

• The MATLAB function that is associated with and executes on behalf of the HDL instance

• Timing specifications and other control data that specifies when the module's MATLAB function is to be called

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Linking with Simulink and the HDL Simulator

When linked with Simulink, the HDL simulator functions as the server, as shown in the following figure.

In this case, the HDL simulator responds to simulation requests it receives from cosimulation blocks in a Simulink model. You begin a cosimulation session from Simulink. After a session is started, you can use Simulink and the HDL simulator to monitor simulation progress and results. For example, you might add signals to an HDL simulator Wave window to monitor simulation timing diagrams.

Using the Block Parameters dialog box for an HDL Cosimulation block, you can configure the following:

• Block input and output ports that correspond to signals (including internal signals) of an HDL module. You can specify sample times and fixed-point data types for individual block output ports if desired.

• Type of communication and communication settings used for exchanging data between the simulation tools.

• Rising-edge or falling-edge clocks to apply to your module. The period of each clock is individually specifiable.

• Tcl commands to run before and after the simulation.

EDA Simulator Link MQ software equips the HDL simulator with a set of customized command extensions. Using the supplied command extension vsimulink, you execute the HDL simulator with an instance of an HDL module for cosimulation with Simulink. After the module is loaded, you can start the cosimulation session from Simulink.

EDA Simulator Link MQ software also includes a block for generating value change dump (VCD) files. You can use VCD files generated with this block to perform the following tasks:

• View Simulink simulation waveforms in your HDL simulation environment

• Compare results of multiple simulation runs, using the same or different simulation environments

• Use as input to post-simulation analysis tools

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Communicating with MATLAB or Simulink and the HDL Simulator

The mode of communication that you use for a link between the HDL simulator and MATLAB or Simulink depends on whether your simulation application runs in a local, single-system configuration or in a network configuration. If the HDL simulator and The MathWorks products can run locally on the same system and your application requires only one communication channel, you have the option of choosing between shared memory and TCP/IP socket communication. Shared memory communication provides optimal performance and is the default mode of communication.

TCP/IP socket mode is more versatile. You can use it for single-system and network configurations. This option offers the greatest scalability. For more on TCP/IP socket communication, see TCP/IP Socket Communication.

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Getting Started

Requirements