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Gaining Access to and Applying Port Information

EDA Simulator Link software passes information about the entity or module under test in the portinfo structure. The portinfo structure is passed as the third argument to the function. It is passed only in the first call to your MATLAB function. You can use the information passed in the portinfo structure to validate the entity or module under simulation. Three fields supply the information, as indicated in the next sample. . The content of these fields depends on the type of ports defined for the VHDL entity or Verilog module.

portinfo.field1.field2.field3

The following table lists possible values for each field and identifies the port types for which the values apply.

HDL Port Information

Field...Can Contain...Which...And Applies to...
field1inIndicates the port is an input portAll port types
outIndicates the port is an output portAll port types
inoutIndicates the port is a bidirectional port All port types
tscaleIndicates the simulator resolution limit in seconds as specified in the HDL simulatorAll types
field2portnameIs the name of the portAll port types
field3type

Identifies the port type

For VHDL: integer, real, time, or enum

For Verilog: 'verilog_logic' identifies port types reg, wire, integer

All port types
right

(VHDL only)

The VHDL RIGHT attribute VHDL integer, natural, or positive port types
left

(VHDL only)

The VHDL LEFT attribute VHDL integer, natural, or positive port types
 size

VHDL: The size of the matrix containing the data

Verilog: The size of the bit vector containing the data

All port types
label

VHDL: A character literal or label

Verilog: the string '01ZX'

VHDL: Enumerated types, including predefined types BIT, STD_LOGIC, STD_ULOGIC, BIT_VECTOR, and STD_LOGIC_VECTOR

Verilog: All port types

The first call to the MATLAB function has three arguments including the portinfo structure. Checking the number of arguments is one way that you can ensure that portinfo was passed. For example:

if(nargin ==3)
 tscale  = portinfo.tscale;
end
  


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