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| Contents | Index |
| Learn more about EDA Link Simulator |
To open the block parameters dialog box for the HDL Cosimulation block, double-click the block icon.
Simulink displays the following Block Parameters dialog box.
The first step to configuring your EDA Simulator Link Cosimulation block is to map signals and signal instances of your HDL design to port definitions in your HDL Cosimulation block. In addition to identifying input and output ports, you can specify a sample time for each output port. You can also specify a fixed-point data type for each output port.
The signals that you map can be at any level of the HDL design hierarchy.
To map the signals, you can perform either of the following actions:
Enter signal information manually into the Ports pane of the HDL Cosimulation Block Parameters dialog box (see Entering Signal Information Manually). This approach can be more efficient when you want to connect a small number of signals from your HDL model to Simulink.
Use the Auto Fill button to obtain signal information automatically by transmitting a query to the HDL simulator. This approach can save significant effort when you want to cosimulate an HDL model that has many signals that you want to connect to your Simulink model. However, in some cases, you will need to edit the signal data returned by the query. See Obtaining Signal Information Automatically from the HDL Simulator for details.
Note Verify that signals used in cosimulation have read/write access. You can check read/write access through the HDL simulator—see product documentation for details. This rule applies to all signals on the Ports, Clocks, and Tcl panes. |
These rules are for signal/port and module path specifications in Simulink. Other specifications may work but are not guaranteed to work in this or future releases.
HDL designs generally do have hierarchy; that is the reason for this syntax. This specification does not represent a file name hierarchy.
Path specifications must follow the rules listed in the following sections:
Path Specifications for Simulink Cosimulation Sessions with Verilog Top Level
Path Specifications for Simulink Cosimulation Sessions with VHDL Top Level
Path Specifications for Simulink Cosimulation Sessions with Verilog Top Level.
Path specification must start with a top-level module name.
Path specification can include "." or "/" path delimiters, but cannot include a mixture.
The leaf module or signal must match the HDL language of the top-level module.
The following examples show valid signal and module path specifications:
top.port_or_sig /top/sub/port_or_sig top top/sub top.sub1.sub2
The following examples show invalid signal and module path specifications:
top.sub/port_or_sig
Why this specification is invalid: You cannot use mixed delimiters.
:sub:port_or_sig
:
:sub
Why this specification is invalid: When you use VHDL-specific delimiters you limit the interoperability with paths when moving between HDL simulators and between VHDL and Verilog.
Path Specifications for Simulink Cosimulation Sessions with VHDL Top Level.
Path specification may include the top-level module name but it is not required.
Path specification can include "." or "/" path delimiters, but cannot include a mixture.
The leaf module or signal must match the HDL language of the top-level module.
The following examples show valid signal and module path specifications:
top.port_or_sig /sub/port_or_sig top top/sub top.sub1.sub2
The following examples show invalid signal and module path specifications:
top.sub/port_or_sig
Why this specification is invalid: You cannot use mixed delimiters.
:sub:port_or_sig
:
:sub
Why this specification is invalid: When you use VHDL-specific delimiters you limit the interoperability with paths when moving between HDL simulators and between VHDL and Verilog.
The Auto Fill button lets you begin an HDL simulator query and supply a path to a component or module in an HDL model under simulation in the HDL simulator. Usually, some change of the port information is required after the query completes. You must have the HDL simulator running with the HDL module loaded for Auto Fill to work.
The following example describes the required steps.
The example is based on a modified copy of the Manchester Receiver model, in which all signals were first deleted from the Ports and Clocks panes.
Open the block parameters dialog box for the HDL Cosimulation block. Click the Ports tab. The Ports pane opens.
Click the Auto Fill button. The Auto Fill dialog box opens.
This modal dialog box requests an instance path to a component or module in your HDL model; here you enter an explicit HDL path into the edit field. The path you enter is not a file path and has nothing to do with the source files.
In this example, the Auto Fill feature obtains port data for a VHDL component called manchester. The HDL path is specified as /top/manchester.
Click OK to dismiss the dialog box and the query is transmitted.
After the HDL simulator returns the port data, the Auto Fill feature enters it into the Ports pane, as shown in the following figure.
Click Apply to commit the port additions.
The preceding figure shows that the query entered clock, clock enable, and reset ports (labeled clk, enable, and reset respectively) into the ports list. In this example, the clk signal is entered in the Clocks pane, and the enable and reset signals are deleted from the Ports pane, as the next figures show.
Auto Fill returns default values for output ports:
Sample time: 1
Data type: Inherit
Fraction length: Inherit
You may need to change these values as required by your model. In this example, the Sample time should be set to 10 for all outputs. See also Specifying the Signal Data Types.
Before closing the HDL Cosimulation block parameters dialog box, click Apply to commit any edits you have made.
Observe that Auto Fill returned information about all inputs and outputs for the targeted component. In many cases, this will include signals that function in the HDL simulator but cannot be connected in the Simulink model. You may delete any such entries from the list in the Ports pane if they are unwanted. You can drive the signals from Simulink; you just have to define their values by laying down Simulink blocks.
Note that Auto Fill does not return information for internal signals. If your Simulink model needs to access such signals, you must enter them into the Ports pane manually. For example, in the case of the Manchester Receiver model, you would need to add output port entries for top/manchester/sync_i, top/manchester/isum_i, and top/manchester/qsum_i, as shown in step 8.
Note that clk, reset, and clk_enable may be in the Clocks and Tcl panes but they don't have to be. These signals can be ports if you choose to drive them explicitly from Simulink.
Note When you import VHDL signals using Auto Fill, the HDL simulator returns the signal names in all capitals. |
To enter signal information directly in the Ports pane, perform the following steps:
In the HDL simulator, determine the signal path names for the HDL signals you plan to define in your block.
For example, the following shows all signals are subordinate to the top-level module manchester.
In Simulink, open the block parameters dialog box for your HDL Cosimulation block, if it is not already open.
Select the Ports pane tab. Simulink displays the following dialog box.
In this pane, you define the HDL signals of your design that you want to include in your Simulink block and set a sample time and data type for output ports. The parameters that you should specify on the Ports pane depend on the type of device the block is modeling as follows:
For a device having both inputs and outputs: specify block input ports, block output ports, output sample times and output data types.
For output ports, accept the default or enter an explicit sample time. Data types can be specified explicitly, or set to Inherit (the default). In the default case, the output port data type is inherited either from the signal connected to the port, or derived from the HDL model.
For a sink device: specify block output ports.
For a source device: specify block input ports.
Enter signal path names in the Full HDL name column by double-clicking on the existing default signal.
Use HDL simulator path name syntax (see Specifying HDL Signal/Port and Module Paths for Cosimulation).
If you are adding signals, click New and then edit the default values. Select either Input or Output from the I/O Mode column.
If you want to, set the Sample Time, Data Type, and Fraction Length parameters for signals explicitly, as discussed in the remaining steps.
When you have finished editing clock signals, click Apply to register your changes with Simulink.
The following dialog box shows port definitions for an HDL Cosimulation block. The signal path names match path names that appear in the HDL simulator wave window.
You must specify a sample time for the output ports. Simulink uses the value that you specify, and the current settings of the Timescales pane, to calculate an actual simulation sample time.
For more information on sample times in the EDA Simulator Link cosimulation environment, see Understanding the Representation of Simulation Time.
You can configure the fixed-point data type of each output port explicitly if desired, or use a default (Inherited). In the default case, Simulink determines the data type for an output port as follows:
If Simulink can determine the data type of the signal connected to the output port, it applies that data type to the output port. For example, the data type of a connected Signal Specification block is known by back-propagation. Otherwise, Simulink queries the HDL simulator to determine the data type of the signal from the HDL module.
To assign an explicit fixed-point data type to a signal, perform the following steps:
Select either Signed or Unsigned from the Data Type column.
If the signal has a fractional part, enter the Fraction Length.
For example, if the model has an 8-bit signal with Signed data type and a Fraction Length of 5, the HDL Cosimulation block assigns it the data type sfix8_En5. If the model has an Unsigned 16-bit signal with no fractional part (a Fraction Length of 0), the HDL Cosimulation block assigns it the data type ufix16.
Before closing the dialog box, click Apply to register your edits.
The Data Type and Fraction Length parameters apply only to output signals. See Data Type and Fraction Length on the Ports pane description of the HDL Cosimulation block.
You configure the timing relationship between Simulink and the HDL simulator by using the Timescales pane of the block parameters dialog box. Before setting the Timescales parameters, you should read Understanding the Representation of Simulation Time to understand the supported timing modes and the issues that will determine your choice of timing mode.
You can specify either a relative or an absolute timing relationship between Simulink and the HDL simulator, as described in Timescales Pane of the HDL Cosimulation block reference.
The differences in the representation of simulation time can be reconciled in one of two ways using the EDA Simulator Link interface:
By defining the timing relationship manually (with Timescales pane)
When you define the relationship manually, you determine how many femtoseconds, picoseconds, nanoseconds, microseconds, milliseconds, seconds, or ticks in the HDL simulator represent 1 second in Simulink.
This quantity of HDL simulator time can be expressed in one of the following ways:
In relative terms (i.e., as some number of HDL simulator ticks). In this case, the cosimulation is said to operate in relative timing mode. The HDL Cosimulation block defaults to relative timing mode for cosimulation. For more on relative timing mode, see Relative Timing Mode.
In absolute units (such as milliseconds or nanoseconds). In this case, the cosimulation is said to operate in absolute timing mode. For more on absolute timing mode, see Absolute Timing Mode.
For more on relative and absolute time, see Understanding the Representation of Simulation Time.
By allowing EDA Simulator Link to define the timescale automatically (with Auto Timescale on the Timescales pane)
When you allow the link software to define the timing relationship, it attempts to set the timescale factor between the HDL simulator and Simulink to be as close as possible to 1 second in the HDL simulator = 1 second in Simulink. If this setting is not possible, the link product attempts to set the signal rate on the Simulink model port to the lowest possible number of HDL simulator ticks.
You can create rising-edge or falling-edge clocks, resets, or clock enable signals that apply internal stimuli to your model under cosimulation. You can add these signals in the following ways:
By Creating Optional Clocks with the Clocks Pane of the HDL Cosimulation Block
By implementing these signals directly in HDL code. If your model is part of a much larger HDL design, you (or the larger model designer) may choose to implement these signals in the Verilog or VHDL files. However, that implementation exceeds the scope of this documentation; see an HDL reference for more information.
Adding Signals Using Simulink Blocks. Add rising-edge or falling-edge clocks, resets, or clock enable signals to your Simulink model using Simulink blocks. See the Simulink User Guide and Reference for instructions on adding Simulink blocks to a Simulink model.
In the following example excerpt, the shaded area shows a clock, a reset, and a clock enable signal as input to a multiple HDL Cosimulation block model. These signals are created using two Simulink data type conversion blocks and a constant source block, which connect to the HDL Cosimulation block labeled "Manchester Receiver Subsystem".
Creating Optional Clocks with the Clocks Pane of the HDL Cosimulation Block. When you specify a clock in your block definition, Simulink creates a rising-edge or falling-edge clock that drives the specified HDL signal.
Simulink attempts to create a clock that has a 50% duty cycle and a predefined phase that is inverted for the falling edge case. If necessary, Simulink degrades the duty cycle to accommodate odd Simulink sample times, with a worst case duty cycle of 66% for a sample time of T=3.
Whether you have configured the Timescales pane for relative timing mode or absolute timing mode, the following restrictions apply to clock periods:
If you specify an explicit clock period, you must enter a sample time equal to or greater than 2 resolution units (ticks).
If the clock period (whether explicitly specified or defaulted) is not an even integer, Simulink cannot create a 50% duty cycle, and therefore the EDA Simulator Link software creates the falling edge at
(rounded down to the nearest integer).
For more information on calculating relative and absolute timing modes, see Defining the Simulink and HDL Simulator Timing Relationship.
The following figure shows a timing diagram that includes rising and falling edge clocks with a Simulink sample time of T=10 and an HDL simulator resolution limit of 1 ns. The figure also shows that given those timing parameters, the clock duty cycle is 50%.
To create clocks, perform the following steps:
In the HDL simulator, determine the clock signal path names you plan to define in your block. To do so, you can use the same method explained for determining the signal path names for ports in step 1 of Mapping HDL Signals to Block Ports.
Select the Clocks tab of the Block Parameters dialog box. Simulink displays the dialog box as shown in the next figure.
Click New to add a new clock signal.
Edit the clock signal path name directly in the table under the Full HDL Name column by double-clicking the default clock signal name (/top/clk). Then, specify your new clock using HDL simulator path name syntax. See Specifying HDL Signal/Port and Module Paths for Cosimulation.
The HDL simulator does not support vectored signals in the Clocks pane. Signals must be logic types with 1 and 0 values.
To specify whether the clock generates a rising-edge or falling edge signal, select Rising or Falling from the Active Clock Edge list.
The Period field specifies the clock period. Accept the default (2), or override it by entering the desired clock period explicitly by double-clicking in the Period field.
Specify the Period field as an even integer, with a minimum value of 2.
When you have finished editing clock signals, click Apply to register your changes with Simulink.
The following dialog box defines the rising-edge clock clk for the HDL Cosimulation block, with a default period of 2.
Driving Signals by Adding Force commands. Drive clocks, resets, and enable signals by adding force commands to the Tcl pane.
For example:
force /iqconv/clk 1 0, 0 5 ns -repeat 10 ns force /iqconv/clk_enable 1 force /iqconv/reset 1
You can also drive signals with vsim and the force command.
For example:
vsim('tclstart', {'force /iqconv/clk 1 0, 0 5 ns -repeat 10 ns ',
'force /iqconv/clk_enable 1', 'force /iqconv/reset 1'});You must select shared memory or socket communication (see Communicating with MATLAB or Simulink and the HDL Simulator).
After you decide, configure a block's communication link with the Connection pane of the block parameters dialog box.
The following steps guide you through the communication configuration:
Determine whether Simulink and the HDL simulator are running on the same computer. If they are, skip to step 4.
Clear the The HDL simulator is running on this computer check box. (This check box defaults to selected.) Because Simulink and the HDL simulator are running on different computers, Connection method is automatically set to Socket.
Enter the host name of the computer that is running your HDL simulation (in the HDL simulator) in the Host name text field. In the Port number or service text field, specify a valid port number or service for your computer system. For information on choosing TCP/IP socket ports, see Choosing TCP/IP Socket Ports. Skip to step 5.
If the HDL simulator and Simulink are running on the same computer, decide whether you are going to use shared memory or TCP/IP sockets for the communication channel. For information on the different modes of communication, see Communicating with MATLAB or Simulink and the HDL Simulator.
If you choose TCP/IP socket communication, specify a valid port number or service for your computer system in the Port number or service text field. For information on choosing TCP/IP socket ports, see Choosing TCP/IP Socket Ports.
If you choose shared memory communication, select the Shared memory check box.
If you want to bypass the HDL simulator when you run a Simulink simulation, use the Connection Mode options to specify what type of simulation connection you want. Select one of the following options:
Full Simulation: Confirm interface and run HDL simulation (default).
Confirm Interface Only: Check HDL simulator for proper signal names, dimensions, and data types, but do not run HDL simulation.
No Connection: Do not communicate with the HDL simulator. The HDL simulator does not need to be started.
With the second and third options, EDA Simulator Link software does not communicate with the HDL simulator during Simulink simulation.
Click Apply.
The following example dialog box shows communication definitions for an HDL Cosimulation block. The block is configured for Simulink and the HDL simulator running on the same computer, communicating in TCP/IP socket mode over TCP/IP port 4449.
You have the option of specifying Tcl commands to execute before and after the HDL simulator simulates the HDL component of your Simulink model. Tcl is a programmable scripting language supported by most HDL simulation environments. Use of Tcl can range from something as simple as a one-line puts command to confirm that a simulation is running or as complete as a complex script that performs an extensive simulation initialization and startup sequence. For example, you can use the Post- simulation command field on the Tcl Pane to instruct the HDL simulator to restart at the end of a simulation run.
You can specify the pre-simulation and post-simulation Tcl commands by entering Tcl commands in the Pre-simulation commands or Post-simulation commands text fields of the HDL Cosimulation block.
To specify Tcl commands, perform the following steps:
Select the Tcl tab of the Block Parameters dialog box. The dialog box appears as follows.
The Pre-simulation commands text box includes an puts command for reference purposes.
Enter one or more commands in the Pre-simulation command and Post-simulation command text boxes. You can specify one Tcl command per line in the text box or enter multiple commands per line by appending each command with a semicolon (;), which is the standard Tcl concatenation operator.
Alternatively, you can create a ModelSim DO file that lists Tcl commands and then specify that file with the ModelSim do command as shown in the following figure.
Click Apply.
One way to control block parameters is through the HDL Cosimulation block graphical dialog box. However, you can also control blocks by programmatically controlling the mask parameter values and the running of simulations. Parameter values can be read using the Simulink get_param function and written using the Simulink set_param function. All block parameters have attributes that indicate whether they are:
Tunable — The attributes can change during the simulation run.
Evaluated — The parameter string value undergoes an evaluation to determine its actual value used by the S-Function.
The HDL Cosimulation block does not have any tunable parameters; thus, you get an error if you try to change a value while the simulation is running. However, it does have a few evaluated parameters.
You can see the list of parameters and their attributes by performing a right-mouse click on the block, selecting View Mask, and then the Parameters tab. The Variable column shows the programmatic parameter names. Alternatively, you can get the names programmatically by selecting the HDL Cosimulation block and then typing the following commands at the MATLAB prompt:
>> get_param(gcb, 'DialogParameters')
Some examples of using MATLAB to control simulations and mask parameter values follow. Usually, the commands are put into an M-script or M-function file and automatically called by several callback hooks available to the model developer. You can place the code in any of these suggested locations, or anywhere you choose:
In the model workspace, for example, View > Model Explorer > Simulink Root > model_name > Model Workspace > Data Source is M-Code.
In a model callback, for example, File > Model Properties > Callbacks.
A subsystem callback (right-mouse click on an empty subsystem and then select Block Properties > Callbacks). Many of the EDA Simulator Link demos use this technique to start the HDL simulator by placing M-code in the OpenFcn callback.
The HDL Cosimulation block callback (right-mouse click on HDL Cosimulation block, and then select Block Properties > Callbacks).
In a regression environment, you may need to determine the socket number for the Simulink/HDL simulator connection during the simulation to avoid collisions with other simulation runs. This example shows code that could handle that task. The script is for a 32-bit Linux platform.
ttcp_exec = [matlabroot '/toolbox/shared/hdllink/scripts/ttcp_glnx'];
[status, results] = system([ttcp_exec ' -a']);
if ~s
parsed_result = strread(results,'%s');
avail_port = parsed_result{2};
else
error(results);
end
set_param('MyModel/HDL Cosimulation', 'CommPortNumber', avail_port);
 | Add the HDL Cosimulation Block to the Simulink Test Bench Model | Start the HDL Simulation |  |
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