| Version 1.3 (R14SP1+) Link for ModelSim® Release Notes | |
This table summarizes what's new in V1.3 (R14SP1+):
| New Features and Changes | Version Compatibility Considerations | Fixed Bugs and Known Problems | Related Documentation at Web Site |
|---|---|---|---|
| Yes Details below | Yes—Details labeled as Compatibility Considerations, below. See also Summary. | No bug fixes | No |
New features and changes introduced in this version are:
Link for ModelSim 1.3 lets you define the timing relationship between Simulink and ModelSim during cosimulation. Using the new Timescales pane of the VHDL Cosimulation block, you can now overcome problems caused by differences in the representation of simulation time between ModelSim and Simulink.
In ModelSim, the unit of simulation time is referred to as a tick. The duration of a tick is defined by the ModelSim resolution limit. The default resolution limit is 1 ns. In Simulink, simulation time is represented as a double-precision value scaled to seconds. This representation accommodates continuous models and discrete controllers.
In previous releases, the VHDL Cosimulation block supported only a fixed correspondence between simulation time in Simulink and ModelSim. In the older timing mode, one time step in Simulink corresponded to one tick in ModelSim. For example, if the total simulation time in Simulink were specified as 100 time steps, then the ModelSim VHDL simulation would run for exactly 100 ticks (i.e., 100 ns at the default resolution limit).
Link for ModelSim 1.3 continues to support the older timing model as a default. However, the new Timescales pane of the VHDL Cosimulation block lets you specify the relationship between timestep sizes in a Simulink/ModelSim cosimulation with much more control and flexibility.
The figure below shows the default settings of the Timescales pane.
The Timescales pane specifies a correspondence between one second of Simulink time and some quantity of ModelSim time. This quantity of ModelSim time can be expressed in one of the following ways:
In relative terms (i.e., as some number of ModelSim ticks). In this case, the cosimulation is said to operate in relative timing mode. In relative timing mode, one second in Simulink corresponds to N ticks in ModelSim, where N is a scale factor.
Relative timing mode is the default.
In absolute units (such as milliseconds or nanoseconds). In this case, the cosimulation is said to operate in absolute timing mode. In absolute timing mode, one second in Simulink corresponds to (N * Tu) seconds in ModelSim, where Tu is an absolute time unit (e.g., ms, ns, etc.) and N is a scale factor.
The Timescales pane contains two lists that let you select the timing mode or time unit and the scale factor. The list on the right specifies the timing mode or the time unit (see the figure below). To choose relative mode, select Tick. To choose absolute mode, select one of the available time units ( fs, ps, ns, us, ms, or s ).
The list on the left specifies the scale factor applied to the time unit (see the figure below).
The default Timescales settings (see above) specify relative mode with a scale factor of 1. This default Simulink / ModelSim timing relationship is the same as the relationship defined in previous releases. The default ensures backward compatibility for existing models.
In the figure below, the Timescales parameters are configured for absolute mode. An absolute time unit (fs) and a scale factor of 100 are selected. During cosimulation, one second in Simulink corresponds to 10 fs in ModelSim.
Representation of Simulation Time in the Link for ModelSim documentation gives a detailed description of the Timescales pane and the supported timing modes, with cosimulation examples.
Link for ModelSim now supports ModelSim Version 6.0.
You can now copy HDL signal names (including the full HDL signal path) from the ModelSim wave window and paste them directly into the Full HDL Name field of the Ports or Clocks pane of the VHDL Cosimulation block. This convenience can save you time and errors when cosimulating an HDL design that includes long or complex signal pathnames.
To copy and paste a signal name:
Activate ModelSim. Select the desired signal from the signal list in the ModelSim wave window. In the figure below, the signal /inverter/inport is selected.
Right-click on the selected signal. Then select Copy from the context menu.
Activate Simulink. Then open the block parameters dialog for the desired VHDL Cosimulation block in your model.
Activate the appropriate (Ports or Clocks) pane of the VHDL Cosimulation block.
Select the desired signal entry from the signal list, or click the New button to create a new entry.
Select the Full HDL Name field.
Right-click and select Paste from the context menu to paste the signal name into the Full HDL Name field. At this point, the signal name is in a special clipboard format (shown below).
Click Update. Link for ModelSim translates the signal name into its final format (in this example, /inverter/inport ) and updates the signal list.
If required, configure other parameters of the signal.
Click Apply when you have finished entering signal data.
The VHDL Cosimulation block no longer supports use of -1 block output port sample time or clock period.
In previous releases, you could assign the default value -1 as
The sample time for VHDL Cosimulation block output ports
The clock period for time for VHDL Cosimulation block clocks
When this default was assigned, Simulink set the port sample time or the clock period equal to the fastest sample time used in the block.
You must explicitly specify sample times for all VHDL Cosimulation block output ports and clock periods, or accept default values. Default values are
1 for output port sample times
2 for clock periods
VHDL Cosimulation blocks in existing models should be modified to specify explicit output port sample times and clock periods. Use of the value -1 will cause an error at simulation time.
The VHDL Source and VHDL Sink blocks have been removed from the Link for ModelSim block library. These blocks were simply VHDL Cosimulation blocks that were preconfigured with only output ports (Source block) or only input ports (Sink block).
Existing models that use VHDL Source and VHDL Sink blocks will continue to operate correctly, using the Simulink block forwarding mechanism. However, we recommend that you change existing models to use VHDL Cosimulation blocks rather than VHDL Source and VHDL Sink blocks.
The setupmodelsim command has been renamed to configuremodelsim. The two commands are functionally identical.
For backward compatibility, the setupmodelsim command continues to work in this release. However, we recommend that you replace setupmodelsim in your scripts, using configuremodelsim instead.
| Version 1.3.1 (R14SP2) Link for ModelSim® | Version 1.2 (R14SP1) Link for ModelSim® | |
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