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wrapverilog - (For ModelSim) Apply VHDL wrapper to Verilog module

Syntax

wrapverilog [-nocompile] <verilog_module>

Description

Note   EDA Simulator Link now supports Verilog models directly, without requiring a VHDL wrapper. All EDA Simulator Link MATLAB functions, and the HDL Cosimulation block, offer the same language-transparent feature set for both Verilog and VHDL models. The wrapverilog function is supported for backward compatibility, and is still in use by many EDA Simulator Link demos.

The wrapverilog command applies a VHDL wrapper to the specified Verilog module and then automatically compiles the resulting VHDL file. You can then use your wrapped Verilog module with EDA Simulator Link.

This command is issued in the HDL simulator.

Before executing the wrapverilog command on a Verilog file, you must compile and load the Verilog module in ModelSim, as in the following example.

vlib work
vmap work work
vlog myverilogmod.v 
vsim myverilogmod 
wrapverilog [-nocompile] myverilogmod 

Arguments

<verilog_module>

Specifies the Verilog module to which a VHDL wrapper is to be applied. The module you specify must be in a valid ModelSim design library when you issue the command.

-nocompile

Suppresses automatic compilation of the resulting VHDL file, verilog_module_wrap.vhd.

Examples

The following command applies a VHDL wrapper to Verilog module myverilogmod.v and writes the output to myverilogmod_wrap.vhd. The -nocompile option suppresses automatic compilation.

ModelSim> wrapverilog -nocompile myverilogmod 

vsimulink

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