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Learn more about Filter Design HDL Coder   

Setting the Names and Location for Generated HDL Files

Default File Names and Locations

By default, the coder creates the HDL files listed in the following table and places them in subdirectory hdlsrc under your current working directory. File names in generated HDL code derive from the name of the filter for which the HDL code is being generated and the file type extension .vhd or .v for VHDL and Verilog, respectively. The table lists example file names based on filter name Hq.

LanguageGenerated FileFile NameExample
VerilogSource file for the quantized filterdfilt_name.vHq.v
Source file for the filter's test benchdfilt_name_tb.vHq_tb.v
VHDLSource file for the quantized filterdfilt_name.vhdHq.vhd
Source file for the filter's test benchdfilt_name_tb.vhdHq_tb.vhd
Package file, if required by the filter designdfilt_name_pkg.vhdHq_pkg.vhd

The coder also uses the filter name to name the VHDL entity or Verilog module that represents the quantized filter in the HDL code. Assuming a filter name of Hd, the name of the filter entity or module in the HDL code is Hd.

By default, the code for a filter's VHDL entity and architectures is written to a single VHDL source file. Alternatively, you can specify that the coder write the generated code for the entity and architectures to separate files. For example, if the filter name is Hd, the coder writes the VHDL code for the filter to files Hd_entity.vhd and Hd_arch.vhd (see Splitting Entity and Architecture Code into Separate Files).

By default, the coder generates a single test bench file, containing all test bench helper functions, data, and test bench code. You can split these elements into separate files, as described in Splitting Test Bench Code and Data into Separate Files.

Setting Filter Entity and General File Naming Strings

To set the string that the coder uses to name the filter entity or module and generated files, specify a new value in the Name field of the Filter settings pane of the Generate HDL dialog box. The coder uses the Name string to

By default, the filter HDL files are generated with a .vhd or .v file extension, depending on the language selection. To change the file extension,

  1. Select the Global Settings tab on the Generate HDL dialog box.

  2. Select the General tab in theAdditional settings pane.

  3. Type the new file extension in the Verilog file extension or VHDL file extension field.

Based on the following settings, the coder generates the filter file MyFIR.vhdl.

Command Line Alternative: Use the generatehdl and generatetb functions with the Name property to set the name of your filter entity and the base string for generated HDL file names. Specify the functions with the VerilogFileExtension or VHDLFileExtension property to specify a file type extension for generated HDL files.

Setting the Location of Generated Files

By default, the coder places all generated HDL files in the subfolder hdlsrc under your current working folder. To direct the coder output to a folder other than the default target folder, you can use either the Folder field or the Browse button in the Target pane of the Generate HDL dialog box.

Clicking on the Browse button opens a browser window that lets you select (or create) the folder to which generated code will be written. When the folder is selected, the full path and folder name are automatically entered into the Folder field.

Alternatively, you can enter the folder specification directly into the Folder field. If you specify a folder that does not exist, the coder creates the folder for you before writing the generated files. Your folder specification can be one of the following:

In the following figure, the folder is set to MyFIRBetaVHDL.

Given this setting, the coder creates the subfolder MyFIRBetaVHDL under the current working folder and writes generated HDL files to that folder.

Command Line Alternative: Use the generatehdl and generatetb functions with theTargetDirectory property to redirect coder output.

Setting the Postfix String for VHDL Package Files

By default, the coder appends the postfix _pkg to the base file name when generating a VHDL package file. To rename the postfix string for package files, do the following:

  1. Select the Global Settings tab on the Generate HDL dialog box.

  2. Select the General tab in theAdditional settings pane.

  3. Specify a new value in the Package postfix field.

      Note   When specifying a string for use as a postfix in file names, consider the size of the base name and platform-specific file naming requirements and restrictions.

Command Line Alternative: Use the generatehdl and generatetb functions with the PackagePostfix property to rename the file name postfix for VHDL package files.

Splitting Entity and Architecture Code into Separate Files

By default, the coder includes a filter's VHDL entity and architecture code in the same generated VHDL file. Alternatively, you can instruct the coder to place the entity and architecture code in separate files. For example, instead of all generated code residing in MyFIR.vhd, you can specify that the code reside in MyFIR_entity.vhd and MyFIR_arch.vhd.

The names of the entity and architecture files derive from

To split the filter source file, do the following:

  1. Select the Global Settings tab on the Generate HDL dialog box.

  2. Select the General tab in theAdditional settings pane.

  3. Select Split entity and architecture. The Split entity file postfix and Split arch. file postfix fields are now enabled.

  4. Specify new strings in the postfix fields if you want to use postfix string values other than _entity and _arch to identify the generated VHDL files.

      Note   When specifying a string for use as a postfix value in file names, consider the size of the base name and platform-specific file naming requirements and restrictions.

Command Line Alternative: Use the generatehdl and generatetb functions with the property SplitEntityArch to split the filter's VHDL code into separate files. Use properties SplitEntityFilePostfix and SplitArchFilePostfix to rename the file name postfix for VHDL entity and architecture code components.

  


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