Filter Design HDL Coder™

Testing with an HDL Test Bench

Overview

If you generate VHDL or Verilog test bench code, you can use a simulator of your choice to verify your filter design. For example purposes, the following sections explain how to apply generated HDL test bench code by using the Mentor Graphics ModelSim simulator, in the following steps:

1. Generate the filter and test bench HDL code.

2. Start the simulator.

3. Compile the generated filter and test bench files.

4. Run the test bench simulation.

Note   Due to differences in representation of double-precision data in VHDL and Verilog, restrictions apply to the types of test benches that are interoperable. The following table shows valid and invalid test bench type and HDL combinations when code is generated for a double-precision filter. Test Bench Type VHDL Verilog VHDL Valid Invalid Verilog Invalid Valid These restrictions do not apply for fixed-point filters.

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Generating the Filter and Test Bench HDL Code

Use the Filter Design HDL Coder GUI or command line interface to generate the HDL code for your filter design and test bench. As explained in Specifying a Test Bench Type, the GUI generates a VHDL or Verilog test bench file by default, depending on your language selection. To specify a language-specific test bench type explicitly, select the VHDL file or Verilog file option in the Test bench settings pane of the Generate HDL dialog box. You can specify a number of other test bench customizations, as described in Customizing the Test Bench.

The following figure shows settings for generating the filter and test bench files MyFilter.vhd, MyFilter_tb.vhd, and MyFilter_tb.v. The dialog box also specifies that the generated files are to be placed in the default target directory hdlsrc under the current working directory.

After you click Generate, the coder displays progress information similar to the following in the MATLAB Command Window:

### Starting VHDL code generation process for filter: Myfilter
### Generating: d:\work\MyPlayArea\hdlsrc\Myfilter.vhd
### Starting generation of Myfilter VHDL entity
### Starting generation of Myfilter VHDL architecture
### HDL latency is 2 samples
### Successful completion of VHDL code generation process for filter: Myfilter

### Starting generation of VHDL Test Bench
### Generating input stimulus
### Done generating input stimulus; length 3429 samples.
### Generating: d:\work\MyPlayArea\hdlsrc\MyFilter_tb.vhd
### Please wait .........
### Done generating VHDL test bench.

### Starting generation of Verilog Test Bench
### Generating input stimulus
### Done generating input stimulus; length 3429 samples.
### Generating: d:\work\MyPlayArea\hdlsrc\MyFilter_tb.vhd
### Please wait .........
### Done generating Verilog test bench.

Note   The length of the input stimulus samples varies from filter to filter. For example, the value 3429 in the preceding message sequence is not fixed; the value is dependent on the filter under test.

If you use the command line interface, you must

• Invoke the functions generatehdl and generatetb, in that order. The order is important because generatetb takes into account additional latency or numeric differences introduced into the filter's HDL code that results from the following property settings.

  Property...	Set to...	Can Affect...
  'AddInputRegister' or 'AddOutputRegister'	'on'	Latency
  'FIRAdderStyle'	'pipeline'	Numeric computations and latency
  'FIRAdderStyle'	'tree'	Numeric computations
  'OptimizeForHDL'	'off'	Numeric computations
  'CastBeforeSum'	'on'	Numeric computations
  'CoeffMultipliers'	'csd' or 'factored-csd'	Numeric computations

• Specify 'VHDL' or 'Verilog' for the TbType parameter. For double-precision filters, you must specify the type that matches the target language specified for your filter code.

• Make sure the property settings specified in the invocation of generatetb match those of the corresponding invocation of generatehdl. You can do this in one of two ways:

  • Omit explicit property settings from the generatetb invocation. This function automatically inherits the property settings established in the generatehdl invocation.

  • Take care to specify the same property settings specified in the generatehdl invocation.

You might also want to consider using the function generatetbstimulus to return the test bench stimulus to the MATLAB Command Window.

For details on the property name and property value pairs that you can specify with the generatehdl and generatetb functions for customizing the output, see Property Reference.

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Starting the Simulator

After you generate your filter and test bench HDL files, start your simulator. When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following appears:

After starting the simulator, set the current directory to the directory that contains your generated HDL files.

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Compiling the Generated Filter and Test Bench Files

Using your choice HDL compiler, compile the generated filter and test bench HDL files. Depending on the language of the generated test bench and the simulator you are using, you might need to complete some precompilation setup. For example, in the Mentor Graphics ModelSim simulator, you might choose to create a design library to store compiled VHDL entities, packages, architectures, and configurations.

The following Mentor Graphics ModelSim command sequence changes the current directory to hdlsrc, creates the design library work, and compiles VHDL filter and filter test bench code. The vlib command creates the design library work and the vcom commands initiate the compilations.

cd hdlsrc
vlib work
vcom MyFilter.vhd
vcom MyFilter_tb.vhd

Note   For VHDL test bench code that has floating-point (double) realizations, use a compiler that supports VHDL-93 or VHDL-02 (for example, in the Mentor Graphics ModelSim simulator, specify the vcom command with the -93 option). Do not compile the generated test bench code with a VHDL-87 compiler. VHDL test benches using double- precision data types do not support VHDL-87, because test bench code uses the image attribute, which is available only in VHDL-93 or higher.

The following screen display shows this command sequence and informational messages displayed during compilation.

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Running the Test Bench Simulation

Once your generated HDL files are compiled, load and run the test bench. The procedure for doing this varies depending on the simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim command. For example:

vsim work.MyFilter_tb

The following display shows the results of loading work.MyFilter_tb with the vsim command.

Once the design is loaded into the simulator, consider opening a display window for monitoring the simulation as the test bench runs. For example, in the Mentor Graphics ModelSim simulator, you might use the add wave * command to open a wave window to view the results of the simulation as HDL waveforms.

To start running the simulation, issue the appropriate simulator command. For example, in the Mentor Graphics ModelSim simulator, you can start a simulation with the run -all command.

The following display shows the add wave * command being used to open a wave window and the -run all command being used to start a simulation.

As your test bench simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the code generation options you applied. For example, a number of HDL customization options allow you to specify settings that can produce numeric results that differ from those produced by the original filter object. For HDL test benches, expected and actual results are compared. If they differ (excluding the specified error margin), an error message similar to the following is returned:

Error in filter test: Expected xxxxxxxx Actual xxxxxxxx

You must determine whether the actual results are expected based on the customizations you specified when generating the filter HDL code.

Note   The failure message that appears in the preceding display is not flagging an error. If the message includes the string Test Complete, the test bench has successfully run to completion. The Failure part of the message is tied to the mechanism the coder uses to end the simulation.

The following wave window shows the simulation results as HDL waveforms.

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Testing a Filter Design

Property Reference