| Filter Design HDL Coder™ | |
As discussed in Customizing Reset Specifications, the coder derives the name of the test bench file from the name of the quantized filter for which the HDL code is being generated and the postfix _tb. The file type extension depends on the type of test bench that is being generated.
| If the Test Bench Is a... | The Extension Is... |
|---|---|
| Verilog file | Defined by the Verilog file extension field in the General pane of the More HDL Settings dialog box |
| VHDL file | Defined by the VHDL file extension field in the General pane of the More HDL Settings dialog box |
The file is placed in the directory defined by the Target directory option in the Filter settings pane of the Generate HDL dialog box.
To specify a test bench name, enter the name in the Name field of the Test bench settings pane, as shown in the following figure.
Note If you enter a string that is a VHDL or Verilog reserved word, the coder appends the reserved word postfix to the string to form a valid identifier. |
Command Line Alternative: Use the generatetb function with the property TestBenchName to specify a name for your filter's test bench.
The coder can generate two types of test benches:
A VHDL file that you can simulate in a simulator of choice
A Verilog file that you can simulate in a simulator of choice
By default, the coder generates a single test bench file, containing all test bench helper functions, data, and test bench code. You can split these elements into separate files, as described in Splitting Test Bench Code and Data into Separate Files.
Because of differences in representation of double-precision data in VHDL and Verilog, restrictions apply to the types of test benches that are interoperable. The following table shows valid and invalid test bench type and HDL combinations when code is generated for a double-precision filter.
| Test Bench Type | VHDL | Verilog |
|---|---|---|
| Verilog | Invalid | Valid |
| VHDL | Valid | Invalid |
Note These restrictions do not apply for fixed-point filters. |
By default, the coder produces a VHDL or Verilog file only, depending on your language selection. If you want to generate additional test bench files, select the desired test bench types listed in the Test bench settings pane of the Generate HDL dialog box.
Command Line Alternative: Use the generatetb function's TbType parameter to specify the type of test bench files to be generated.
By default, the coder generates a single test bench file, containing all test bench helper functions, data, and test bench code. You can split these elements into separate files by selecting the Multi-file test bench option in the More Test Bench Settings dialog box, as shown below.
When you select the Multi-file test bench option, the Test bench data file name postfix option is enabled. The test bench file names are then derived from the name of the test bench, the Test bench name option, and the Test bench data file name postfix option as follows:
TestBenchName_TestBenchDataPostfix
For example, if the test bench name is my_fir_filt, and the target language is VHDL, the default test bench file names are:
my_fir_filt_tb.vhd: test bench code
my_fir_filt_tb_pkg.vhd: helper functions package
my_fir_filt_tb_data.vhd: data package
If the filter name is my_fir_filt and the target language is Verilog, the default test bench file names are:
my_fir_filt_tb.v: test bench code
my_fir_filt_tb_pkg.v: helper functions package
my_fir_filt_tb_data.v: test bench data
Command Line Alternative: Use the generatetb function with the properties MultifileTestBench, TestBenchDataPostFix, and TestBenchName to generate and name separate test bench helper functions, data, and test bench code files.
Based on default settings, the coder configures the clock for a filter test bench such that it
Forces clock enable input signals to active high (1).
Asserts the clock enable signal 1 clock cycle after deassertion of the reset signal.
Forces clock input signals low (0) for a duration of 5 nanoseconds and high (1) for a duration of 5 nanoseconds.
To change these clock configuration settings:
Click More Test Bench Settings in the Test bench settings pane of the Generate HDL dialog box. The More Test Bench Settings dialog box appears.
Make the following configuration changes as needed:
| If You Want to... | Then... |
|---|---|
| Disable the forcing of clock enable input signals | Clear Force clock enable. |
| Disable the forcing of clock input signals | Clear Force clock. |
| Reset the number of nanoseconds during which clock input signals are to be driven low (0) | Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point) in the Clock low time field. |
| Reset the number of nanoseconds during which clock input signals are to be driven high (1) | Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point) in the Clock high time field. |
| Change the delay time elapsed between the deassertion of the reset signal and the assertion of clock enable signal. | Specify a positive integer in the Clock enable delay field. |
The following figure highlights the applicable options.
Click Apply to register the change or OK to register the change and close the dialog box.
Command Line Alternative: Use the generatetb function with the properties ForceClock, ClockHighTime, ClockLowTime, ForceClockEnable, and TestBenchClockEnableDelay to reconfigure the test bench clock.
Based on default settings, the coder configures the reset for a filter test bench such that it
Forces reset input signals to active high (1). (Test bench reset input levels are set by the Reset asserted level option).
Asserts reset input signals for a duration of 2 clock cycles.
Applies a hold time of 2 nanoseconds for reset input signals.
The hold time is the amount of time (after some number of initial clock cycles defined by the Reset length option) that reset input signals are to be held past the clock rising edge. The following figure shows the application of a hold time (thold) for reset input signals when the signals are forced to active high and active low. The default Reset length of 2 clock cycles is shown.
Note The hold time applies to reset input signals only if the forcing of reset input signals is enabled. |
To change the default reset configuration settings,
Click More Test Bench Settings in the Test bench settings pane in the Generate HDL dialog box. The More Test Bench Settings dialog box appears.
Make the following configuration changes as needed:
| If You Want to... | Then... |
|---|---|
| Disable the forcing of reset input signals | Clear Force reset. |
| Change the length of time (in clock cycles) during which reset is asserted | Set Reset length (in clock cycles) to an integer greater than or equal to 0. |
| Change the reset value to active low (0) | Select Active-low from the Reset asserted level menu in the Generate HDL dialog box (see Setting the Asserted Level for the Reset Input Signal). |
| Set the hold time | Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point), representing nanoseconds, in the Hold time field. When the Hold time changes, the Setup time (ns) value (displayed below Hold time) is updated. The Setup time (ns) value computed as (clock period - HoldTime) in nanoseconds. |
The following figure highlights the applicable options.
Click Apply to register the change or OK to register the change and close the dialog box.
Note The hold time and setup time settings also apply to data input signals. |
Command Line Alternative: Use the generatetb function with the properties ForceReset, ResetLength, and HoldTime to reconfigure test bench resets.
By default, the coder applies a hold time of 2 nanoseconds for filter data input signals. The hold time is the amount of time that data input signals are to be held past the clock rising edge. The following figure shows the application of a hold time (thold) for data input signals.
To change the hold time setting,
Click More Test Bench Settings in the Test bench settings pane of the Generate HDL dialog box. The More Test Bench Settings dialog box appears.
Specify a positive integer or double (with a maximum of 6 significant digits after the decimal point), representing nanoseconds, in the Hold time field. In the following figure, the hold time is set to 2 nanoseconds.
Click Apply to register the change.
When the Hold time changes, the Setup time (ns) value (displayed below Hold time) is updated. The Setup time (ns) value is computed as (clock period - HoldTime) in nanoseconds. Setup time (ns) is a display-only field.
Note The hold time and setup time settings also apply to reset input signals, if the forcing of such signals is enabled. |
Command Line Alternative: Use the generatetb function with the property HoldTime to adjust the hold time setting.
Customizations that provide optimizations can generate test bench code that produces numeric results that differ from results produced by the original filter object. These options include:
Optimize for HDL
FIR adder style set to Tree
Add pipeline registers for FIR, asymmetric FIR, and symmetric FIR filters
If you choose to use any of these options, consider setting an error margin for the generated test bench to account for differences in numeric results. The error margin is the number of least significant bits the test bench will ignore when comparing the results. To set an error margin:
Click More Test Bench Settings in the Test bench settings pane of the Generate HDL dialog box. The More Test Bench Settings dialog box appears.
For fixed-point filters, the Error margin (bits) field is initialized to a default value of 4 when it is first enabled.
Specify an integer in the Error margin (bits) field that indicates an acceptable minimum number of bits by which the numeric results can differ before the coder issues a warning. In the following figure, the error margin is set to 3 bits.
Click Apply to register the change or OK to register the change and close the dialog box.
By default, the initial value driven on test bench inputs is 'X' (unknown). Alternatively, you can specify that the initial value driven on test bench inputs is 0, as follows:
Click More Test Bench Settings in the Test bench settings pane of the Generate HDL dialog box. The More Test Bench Settings dialog box appears.
To set an initial test bench input value of 0, select the Initialize test bench inputs option.
To set an initial test bench input value of 'X', clear the Initialize test bench inputs option.
Click Apply to register the change or OK to register the change and close the dialog box.
Command Line Alternative: Use the generatetb function with the InitializeTestBenchInputs property to set the initial test bench input value.
By default, the coder generates a filter test bench that includes stimuli appropriate for the given filter. However, you can adjust the stimuli settings or specify user defined stimuli, if necessary. The following table lists the types of responses enabled by default.
| For Filters... | Default Response Types Include... |
|---|---|
| FIR, FIRT, symmetric FIR, and Antisymmetric FIR | Impulse, step, ramp, chirp, and white noise |
| Farrow | Ramp, random, constant, and user-defined stimuli can be applied to the fractional delay input. See Generating Code for Single-Rate Farrow Filters. |
| All others | Step, ramp, and chirp |
To modify the stimuli that the coder is to include in a test bench, select one or more response types listed in the Test bench settings pane of the Generate HDL dialog box. The following figure highlights this pane of the dialog box.
If you select User defined response, you must also specify an expression or function that returns a vector of values to be applied to the filter. The values specified in the vector are quantized and scaled based on the filter's quantization settings.
Command Line Alternative: Use the generatetb function with the properties TestBenchStimulus and TestBenchUserStimulus to adjust stimuli settings.
Reference signal data is represented as arrays in the generated test bench code. The string specified by Test bench reference postfix is appended to the generated signal names. The default string is _ref.
You can set the postfix string to a value other than _ref. To change the string:
Click More Test Bench Settings in the Test bench settings pane of the Generate HDL dialog box. The Test Bench dialog box appears.
Enter a new string in the Test bench reference postfix field, as shown in the following figure.
Click Apply to register the change, or click OK to register the change and close the dialog box.
Command Line Alternative: Use the generatehdl and generatetb functions with the property TestBenchReferencePostFix to change the postfix string.
The coder supports generation of Simulink® HDL Cosimulation block(s). You can use the generated HDL Cosimulation blocks to cosimulate your filter design using Simulink and one of the EDA Simulator Link™ products, in conjunction with an HDL simulator. To use this feature, your installation must be licensed for one or more of the following products:
EDA Simulator Link MQ
EDA Simulator Link IN
EDA Simulator Link DS
The generated HDL Cosimulation blocks are configured to conform to the port and data type interface of the filter selected for code generation. By connecting an HDL Cosimulation block to a Simulink model in place of the filter, you can cosimulate your design with the desired HDL simulator.
To generate HDL Cosimulation blocks:
Click More Test Bench Settings in the Test bench settings pane of the Generate HDL dialog box. The Test Bench dialog box appears.
Select Generate cosimulation blocks option, as shown in the following figure.
When this option is selected, if your installation is licensed for one or more of the HDL simulation products listed previously, the coder generates and opens a Simulink model that contains an HDL Cosimulation block for each licensed product.
Click Apply to register the change, or click OK to register the change and close the dialog box.
In the Generate HDL dialog box, click Generate to generate HDL and test bench code.
In addition to the usual code files, the coder generates a Simulink model containing one or more HDL Cosimulation blocks. The following figure shows a model containing three HDL Cosimulation blocks, one for each of the supported EDA Simulator Link products.
The generated model is untitled and exists in memory only. Be sure to save it to an appropriate directory if you want to preserve the model and blocks for use in future sessions.
The documentation for each of the EDA Simulator Link products contains a "Preparing for Cosimulation" section, which discusses timing, latency, data typing, frame-based processing, and other issues that may be of concern to you when setting up an HDL cosimulation. You can access this information using one of the following links:
EDA Simulator Link MQ: Preparing for Cosimulation
EDA Simulator Link IN: Preparing for Cosimulation
EDA Simulator Link DS (UNIX platform only): Preparing for Cosimulation
Command Line Alternative: Use the generatetb function with the property GenerateCoSimBlock to generate HDL Cosimulation blocks.
| Generating Code for Single-Rate Farrow Filters | Generating the HDL Code | |
| © 1984-2008- The MathWorks, Inc. - Site Help - Patents - Trademarks - Privacy Policy - Preventing Piracy - RSS |