Filter Design HDL Coder™

Customizing Reset Specifications

Setting the Reset Type for Registers

By default, generated HDL code for registers uses a asynchronous reset logic. Whether you should set the reset type to asynchronous or synchronous depends on the type of device you are designing (for example, FPGA or ASIC) and preference.

The following code fragment illustrates the use of asynchronous resets. Note that the process block does not check for an active clock before performing a reset.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    delay_pipeline (0 To 50) <= (OTHERS => (OTHERS => '0'));
  ELSIF clk'event AND clk = '1' THEN
    IF clk_enable = '1' THEN
      delay_pipeline(0) <= signed(filter_in)
      delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS delay_pipeline_process;

To change the reset type to synchronous, select Synchronous from the Reset type menu in the Filter settings pane of the Generate HDL dialog box.

Code for a synchronous reset follows. This process block checks for a clock event, the rising edge, before performing a reset.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN
  IF rising_edge(clk) THEN
    IF reset = '1' THEN
      delay_pipeline (0 To 50) <= (OTHERS => (OTHERS => '0'));
    ELSIF clk_enable = '1' THEN
      delay_pipeline(0) <= signed(filter_in)
      delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS delay_pipeline_process;

Command Line Alternative: Use the generatehdl and generatetb functions with the property ResetType to set the reset style for your filter's registers.

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Setting the Asserted Level for the Reset Input Signal

The asserted level for the reset input signal determines whether that signal must be driven to active high (1) or active low (0) for registers to be reset in the filter design. By default, the coder sets the asserted level to active high. For example, the following code fragment checks whether reset is active high before populating the delay_pipeline register:

Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
.
.
.

To change the setting to active low, select Active-low from the Reset asserted level menu in the Filter settings pane of the Generate HDL dialog box.

With this change, the IF statement in the preceding generated code changes to

IF reset = '0' THEN

Note   The Reset asserted level setting also determines the rest level for test bench reset input signals.

Command Line Alternative: Use the generatehdl and generatetb functions with the property ResetAssertedLevel to set the asserted level for the filter's reset input signal.

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Setting the Names and Location for Generated HDL Files

Customizing the HDL Code