| Language
Selection |
| □ | | Do you need to adjust the target language setting? | Setting the Target Language |
| File
Naming and Location Specifications |
| □ | | Do you want to specify a unique name, which does not match
the name of the quantized filter, for the VHDL entity or
Verilog module that represents the
filter? | Setting the Names
and Location for Generated HDL Files |
| □ | | Do you want the file
type extension for generated HDL files to be a string other
than .vhd for VHDL or .v for
Verilog? | Setting the Names
and Location for Generated HDL Files |
| Reset Specifications |
| □ | | Do you want to use synchronous
resets? | Setting the Reset Type for
Registers |
| □ | | Do you need the asserted level
of the reset signal to be low (0)? | Setting the Asserted
Level for the Reset Input Signal |
| □ | | Do you need to redefine the duration of the reset signal? | Configuring Resets |
| Header Comment and General Naming Specifications |
| □ | | Do you want to add a specific string,
such as a revision control string, to the end of the header comment block in each generated file? | Specifying a Header
Comment |
| □ | | Do you want a string other than coeff to
be used as the base filter coefficient name? | Specifying a Prefix for
Filter Coefficients |
| □ | | If your filter design requires a VHDL package file, do you want the name of
the generated file to include a string other than _pkg? | Setting the Postfix
String for VHDL Package Files |
| □ | | Do you want a string other than _entity to
be appended to VHDL entity or Verilog module names if duplicate names are detected? | Setting the Postfix String for Resolving Entity or Module Name
Conflicts |
| □ | | Do you want a string other than _rsvd to
be appended to specified names and labels that are HDL
reserved words? | Setting the Postfix String for Resolving HDL Reserved Word
Conflicts |
| □ | | Do you want a string other than _process to
be appended to HDL process names? | Setting the Postfix
String for Process Block Labels |
| □ | | Do you want the coder to write the entity and architecture parts
of generated VHDL code to separate files? | Splitting Entity and
Architecture Code into Separate Files |
| □ | | Do you want a string other than u_ to
be prefixed to component instance names? | Setting a Prefix for
Component Instance Names |
| □ | | Do you want a string other than vector_of_ to
be prefixed to vector names in VHDL
code? | Setting a Prefix for Vector
Names |
| □ | | If the coder writes the entity and architecture parts of VHDL code
to separate files, do you want strings other than _entity and _arch included
in the file names? | Splitting Entity and
Architecture Code into Separate Files |
| Port Specifications |
| □ | | Do you want the coder to use strings
other than filter_in and filter_out to
name HDL ports for the filter's data
input and output signals? | Naming HDL Ports |
| □ | | Do you need the coder to declare the
filter's data input and output ports with
a VHDL type other than STD_LOGIC_VECTOR? | Specifying the
HDL Data Type for Data Ports |
| □ | | Do you want the coder to use strings
other than clk and clk_enable to
name HDL ports for the filter's clock and clock
enable input signals? | Naming HDL Ports |
| □ | | Do you want the coder to use a string
other than reset to name an HDL port for the filter's reset input signals? | Naming HDL Ports |
| □ | | Do you want the coder to add an extra input or output register to support the
filter's HDL input and output ports? | Suppressing
Extra Input and Output Registers |
| Advanced Coding Specifications |
| □ | | Do you want the coder to represent all constants as aggregates? | Representing Constants
with Aggregates |
| □ | | Are you using an EDA tool that does not
support loops? Do you need to unroll
and remove VHDL FOR and GENERATE loops? | Unrolling and Removing
VHDL Loops |
| □ | | Do you want the coder to use the VHDL rising_edge function
to check for rising edges when the
filter is operating on registers? | Using the VHDL rising_edge
Function |
| □ | | Do you want to suppress Verilog time scale directives? | Suppressing Verilog
Time Scale Directives |
| □ | | Do you want the coder to omit configurations from generated VHDL code? Are
you going to create and store the filter's VHDL configurations in
separate VHDL source files? | Suppressing the Generation
of VHDL Inline Configurations |
| □ | | Do you want the coder to use the VHDL
syntax "000000..." to represent concatenated
zeros instead of the type safe representation '0'
& '0'? | Specifying VHDL Syntax
for Concatenated Zeros |
| □ | | Do you want to specify programmable
coefficients for a FIR filter? | Specifying Programmable
Filter Coefficients for FIR Filters |
| □ | | Do you want to specify programmable
coefficients for a IIR filter? | Specifying Programmable
Filter Coefficients for IIR Filters |
| □ | | Do you want the coder to apply typical DSP processor
treatment of input data types when generating code for addition and subtraction operations? | Specifying Input Type
Treatment for Addition and Subtraction Operations |
| □ | | Does your filter design require use of complex coefficients or complex input data?? | Using Complex
Data and Coefficients |
| Optimization Specifications |
| □ | | Do you need numeric
results optimized, even if the results are not bit-true
to the results produced by the original filter object ? | Optimizing Generated Code
for HDL |
| □ | | Do you want the coder to replace multiplier operations by applying canonic signed
digit (CSD) and factored CSD techniques? | Optimizing Coefficient Multipliers |
| □ | | Do you need the coder to optimize the final summation for FIR filters? | Optimizing Final Summation for FIR Filters |
| □ | | Do you need to specify an optimal FIR filter architecture with respect
to speed or chip area? | Speed vs. Area Optimizations
for FIR Filters |
| □ | | Do you need to use a Distributed
arithmetic architecture for a fixed-point FIR filter? | Distributed Arithmetic for FIR Filters |
| □ | | Do you want to optimize your filter's clock rate? | Optimizing the Clock Rate with Pipeline Registers |
| Multirate, Cascade, and Farrow Filter Specifications |
| □ | | Do you need to generate code for a multirate filter ? | Generating Code for Multirate Filters |
| □ | | Do you need to generate code for a polyphase sample rate converter or a multirate Farrow sample rate converter ? | Generating Code for Polyphase Sample Rate Converters
Generating Code for Multirate Farrow Sample Rate Converters |
| □ | | Do you need to generate code for a cascade of filter objects? | Generating Code for Cascade Filters |
| □ | | Do you need to generate code for a Farrow filter?
| Generating Code for Single-Rate Farrow Filters |
| Test Bench Specifications |
| □ | | Do you want the coder to write test
bench helper functions, data, and test bench
code to separate files? | Splitting Test Bench Code and Data into Separate Files |
| □ | | Do you want the generated test bench file to include a string other than _tb? | Setting the Names
and Location for Generated HDL Files |
| □ | | Do you want to generate a VHDL test bench? | Specifying a Test Bench Type |
| □ | | Do you want to generate a Verilog file test bench? | Specifying a Test Bench Type |
| □ | | Are you using a user-defined external
source to force clock enable input
signals to a constant value? | Configuring
the Clock |
| □ | | If the test bench is to force clock enable
input signals, do you want it to force the signals to active low (0)? | Configuring
the Clock |
| □ | | Are you using a user-defined external
source to force clock input signals? | Configuring
the Clock |
| □ | | If the test bench is to force clock input
signals, do you want the signals to be driven
high or low for a duration other
than 5 nanoseconds? | Configuring
the Clock |
| □ | | Do you want to delay
the clock enable signal after the assertion of the reset
signal? | Configuring
the Clock |
| □ | | Are you using a user-defined external
source to force reset input signals? | Configuring Resets |
| □ | | If the test bench is to force reset input
signals, do you want it to force the signals to active
low (0)? | Configuring Resets |
| □ | | If the test bench is to force reset input signals, do you want it to apply
a hold time other than two cycles
plus a hold time of 2 nanoseconds? | Configuring Resets |
| □ | | Do you want to apply a hold
time other than 2 nanoseconds to filter
data input signals? | Setting a Hold Time for Data Input Signals |
| □ | | Do you want to customize the stimulus to
be applied by the test bench? | Setting
Test Bench Stimuli |
| □ | | Do you want to set an initial
value to be driven on test bench inputs? | Setting an Initial
Value for Test Bench Inputs |
| □ | | Do you want to cosimulate your
filter with a third-party HDL simulator?
| Generating HDL Cosimulation
Blocks for Use with HDL Simulators |
| Script
Generation Specifications |
| □ | | Do you want to customize script code that is auto-generated for third-party
EDA tools? | Generating Scripts
for EDA Tools |
| □ | | Do you want to customize script file names for auto-generated EDA tool
scripts? | Generating Scripts
for EDA Tools |
| □ | | Do you want to generate an M-file script that captures your nondefault
option settings? | Capturing Code Generation
Settings to an M-File |
Store 
