Learn more about Filter Design HDL Coder

What Is Generated by Default?

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Default Settings for Generated Files Default Generation of Script Files Default Settings for Register Resets Default Settings for General HDL Code Default Settings for Code Optimizations Default Settings for Test Benches

Default Settings for Generated Files

By default, the coder

• Generates the following files, where Hd is the name of the quantized filter:

  Language	File	Name
  Verilog	Filter source	Hd.v
  	Filter test bench	Hd_tb.v
  VHDL	Filter source	Hd.vhd
  	Package (if needed)	Hd_pkg.vhd
  	Test bench	Hd_tb.vhd

• Places generated files in a subdirectory named hdlsrc, under your current working directory.

• Includes VHDL entity and architecture code in a single source file.

For information on modifying these settings, see What Are Your HDL Requirements? and Setting the Names and Location for Generated HDL Files.

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Default Generation of Script Files

Using the defaults, you can automatically generate scripts for the following third-party Electronic Design Automation (EDA) tools:

• Mentor Graphics ModelSim SE/PE HDL simulator

• The Synplify^® family of synthesis tools

See Generating Scripts for EDA Tools for detailed information on generation and customization of scripts.

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Default Settings for Register Resets

By default, the coder

• Uses an asynchronous reset when generating HDL code for registers.

• Uses an active-high (1) signal for register resets.

For information on modifying these settings, see What Are Your HDL Requirements? and Customizing Reset Specifications.

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Default Settings for General HDL Code

By default, the coder

• Names the generated VHDL entity or Verilog module with the name of the quantized filter.

• Names a filter's HDL ports as follows:

  HDL Port	Name
  Input	filter_in
  Output	filter_out
  Clock input	clk
  Clock enable input	clk_enable
  Reset input	reset
  Fractional delay input (Farrow filters only)	filter_fd

• Sets the data types for HDL ports as follows:

  HDL Port	VHDL Type	Verilog Type
  Clock input	STD_LOGIC	wire
  Clock enable input	STD_LOGIC	wire
  Reset	STD_LOGIC	wire
  Data input	STD_LOGIC_VECTOR	wire
  Data output	STD_LOGIC_VECTOR	wire
  Fractional delay input (Farrow filters only)	STD_LOGIC_VECTOR	wire

• Names coefficients as follows:

  For...	Names Coefficients...
  FIR filters	coeffn, where n is the coefficient number, starting with 1
  IIR filters	coeff_xm_sectionn, where x is a or b, m is the coefficient number, and n is the section number

• When declaring signals of type REAL, initializes the signal with a value of 0.0.

• Places VHDL configurations in any file that instantiates a component.

• In VHDL, uses a type safe representation when concatenating zeros: '0' & '0'...

• In VHDL, applies the statement ELSIF clk'event AND clk='1' THEN to check for clock events.

• In Verilog, uses time scale directives.

• Adds an extra input register and an extra output register to the filter code.

• Appends _process to process names.

• When creating labels for VHDL GENERATE statements:

  • Appends _gen to VHDL section and block names.

  • Names VHDL output assignment blocks with the string outputgen.

For information on modifying these settings, see What Are Your HDL Requirements? and Customizing the HDL Code.

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Default Settings for Code Optimizations

By default, most code optimizations are disabled. The coder

• Generates HDL code that is bit-true to the results produced by the original filter object and is not optimized for performance or space requirements.

• Applies a linear final summation to FIR filters. This is the form of summation explained in most DSP text books.

• For FIR filters, generates a fully parallel architecture (optimal for speed).

• Enables multiplier operations for a filter, as opposed to replacing them with additions of partial products.

For information on modifying these settings, see What Are Your HDL Requirements? and Setting Optimizations.

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Default Settings for Test Benches

By default, the coder generates a VHDL test bench that inherits all the HDL settings that are applied to the filter's HDL code. In addition, the coder generates a test bench that

• Is named filter_tb.vhd.

• Forces clock, clock enable, and reset input signals.

• Forces clock enable and reset input signals to active high.

• Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.

• Forces reset signals for two cycles plus the hold time.

• Applies a hold time of 2 nanoseconds to filter reset and data input signals.

• Applies the following stimulus response types:

  For Filters...	Applies Response Types...
  FIR, FIRT, symmetric FIR, and antisymmetric FIR	Impulse, step, ramp, chirp, and white noise
  All others	Step, ramp, and chirp

For information on modifying these settings, see What Are Your HDL Requirements? and Customizing the Test Bench.

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Opening the Generate HDL Dialog Box

What Are Your HDL Requirements?

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