Filter Design HDL Coder™
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AddInputRegister
AddOutputRegister
AddPipelineRegisters
BlockGenerateLabel
CastBeforeSum
ClockEnableInputPort
ClockEnableOutputPort
ClockHighTime
ClockInputPort
ClockInputs
ClockLowTime
ClockProcessPostfix
CoefficientSource
CoeffMultipliers
CoeffPrefix
DALUTPartition
DARadix
EDAScriptGeneration
EntityConflictPostfix
ErrorMargin
FIRAdderStyle
ForceClock
ForceClockEnable
ForceReset
FracDelayPort
HDLCompileFilePostfix
HDLCompileInit
HDLCompileTerm
HDLCompileVerilogCmd
HDLCompileVHDLCmd
HDLSimCmd
HDLSimFilePostfix
HDLSimInit
HDLSimTerm
HDLSynthCmd
HDLSynthFilePostfix
HDLSynthInit
HDLSynthTerm
HDLSimViewWaveCmd
HoldInputDataBetweenSamples
HoldTime
InlineConfigurations
InputPort
InputType
InstanceGenerateLabel
InstancePrefix
LoopUnrolling
MultifileTestBench
Name
OptimizeForHDL
OutputGenerateLabel
OutputPort
OutputType
PackagePostfix
ReservedWordPostfix
ResetAssertedLevel
ResetInputPort
ResetType
ReuseAccum
SafeZeroConcat
SerialPartition
SimulatorFlags
SplitArchFilePostfix
SplitEntityArch
SplitEntityFilePostfix
TargetDirectory
TargetLanguage
TestbenchCoeffStimulus
TestBenchDataPostFix
TestBenchFracDelayStimulus
TestBenchReferencePostFix
TestBenchName
TestBenchStimulus
TestBenchUserStimulus
UseAggregatesForConst
UserComment
UseRisingEdge
UseVerilogTimescale
VectorPrefix
VerilogFileExtension
VHDLFileExtension
Properties Reference
AddInputRegister
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