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Basic FIR Filter Tutorial

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Designing a Basic FIR Filter in FDATool Quantizing the Basic FIR Filter Configuring and Generating the Basic FIR Filter's VHDL Code Getting Familiar with the Basic FIR Filter's Generated VHDL Code Verifying the Basic FIR Filter's Generated VHDL Code

Designing a Basic FIR Filter in FDATool

This tutorial guides you through the steps for designing a basic quantized discrete-time FIR filter, generating VHDL code for the filter, and verifying the VHDL code with a generated test bench.

This section assumes you are familiar with the MATLAB user interface and the Filter Design & Analysis Tool (FDATool). The following instructions guide you through the procedure of designing and creating a basic FIR filter using FDATool:

1. Start the MATLAB software.

2. Set your current folder to the folder you created in Creating a Folder for Your Tutorial Files.

3. Start the FDATool by entering the fdatool command in the MATLAB Command Window. The Filter Design & Analysis Tool dialog box appears.

   

4. In the Filter Design & Analysis Tool dialog box, check that the following filter options are set:

   Option	Value
   Response Type	Lowpass
   Design Method	FIR Equiripple
   Filter Order	Minimum order
   Options	Density Factor: 20
   Frequency Specifications	Units: Hz Fs: 48000 Fpass: 9600 Fstop: 12000
   Magnitude Specifications	Units: dB Apass: 1 Astop: 80

   These settings are for the default filter design that the FDATool creates for you. If you do not need to make any changes and Design Filter is grayed out, you are done and can skip to Quantizing the Basic FIR Filter.

5. If you modified any of the options listed in step 4, click Design Filter. The FDATool creates a filter for the specified design and displays the following message in the FDATool status bar when the task is complete.

   Designing Filter... Done

   For more information on designing filters with the FDATool, see Using FDATool with Filter Design Toolbox Software in the Filter Design Toolbox documentation.

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Quantizing the Basic FIR Filter

You should quantize filters for HDL code generation. To quantize your filter,

1. Open the basic FIR filter design you created in Designing a Basic FIR Filter in FDATool if it is not already open.

2. Click the Set Quantization Parameters button in the left-side toolbar. The FDATool displays a Filter arithmetic menu in the bottom half of its dialog box.

   

3. Select Fixed-point from the Filter arithmetic list. Then select Specify all from the Filter precision list. The FDATool displays the first of three tabbed panels of quantization parameters across the bottom half of its dialog box.

   

   You use the quantization options to test the effects of various settings with a goal of optimizing the quantized filter's performance and accuracy.

4. Set the quantization parameters as follows:

   Tab	Parameter	Setting
   Coefficients	Numerator word length	16
   	Best-precision fraction lengths	Selected
   	Use unsigned representation	Cleared
   	Scale the numerator coefficients to fully utilize the entire dynamic range	Cleared
   Input/Output	Input word length	16
   	Input fraction length	15
   	Output word length	16
   Filter Internals	Rounding mode	Floor
   	Overflow mode	Saturate
   	Accum. word length	40

5. Click Apply.

For more information on quantizing filters with the FDATool, see Using FDATool with Filter Design Toolbox Software in the Filter Design Toolbox documentation.

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Configuring and Generating the Basic FIR Filter's VHDL Code

After you quantize your filter, you are ready to configure coder options and generate the filter's VHDL code. This section guides you through the procedure for starting the Filter Design HDL Coder GUI, setting some options, and generating the VHDL code and a test bench for the basic FIR filter you designed and quantized in Designing a Basic FIR Filter in FDATool and Quantizing the Basic FIR Filter.

1. Start the Filter Design HDL Coder GUI by selecting Targets > Generate HDL in the FDATool dialog box. The FDATool displays the Generate HDL dialog box.

   

2. Find the Filter Design HDL Coder online help. Use the online help to learn about product details or to get answers to questions as you work with the designer.

   1. In the MATLAB window, click the Help button in the toolbar or click Help > Product Help.

   2. In the Help browser's Contents pane, select the Filter Design HDL Coder entry.

   3. Minimize the Help browser.

3. In the Generate HDL dialog box, click the Help button. A small context-sensitive help window opens. The window displays information about the dialog box.

4. Close the Help window.

5. Place your cursor over the Folder label or text box in the Target pane of the Generate HDL dialog box, and right-click. A What's This? button appears.

   

6. Click What's This? The context-sensitive help window displays information describing the Folder option. Use the context-sensitive help as needed while using the GUI to configure the contents and style of the generated HDL code. A help topic is available for each option.

7. In the Name text box of the Target pane, replace the default name with basicfir. This option names the VHDL entity and the file that is to contain the filter's VHDL code.

   

8. Select the General tab of the Additional settings section of the GUI. Type Tutorial - Basic FIR Filter in the Comment in header text box. The coder adds the comment to the end of the header comment block in each generated file.

   

9. Select the Ports tab of the Additional settings section of the GUI.

   

10. Change the names of the input and output ports. In the Input port text box, replace filter_in with data_in. In the Output port text box, replace filter_out with data_out.

    

11. Clear the check box for the Add input register option. The Ports pane should now look like the following.

    

12. Click on the Test Bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with basicfir_tb. This option names the generated test bench file.

    

13. Click Generate to start the code generation process.

    The coder displays messages in the MATLAB Command Window as it generates the filter and test bench VHDL files:

    ### Starting VHDL code generation process for filter: basicfir
    ### Generating: C:\hdlfilter_tutorials\hdlsrc\basicfir.vhd
    ### Starting generation of basicfir VHDL entity
    ### Starting generation of basicfir VHDL architecture
    ### HDL latency is 2 samples
    ### Successful completion of VHDL code generation process for filter: basicfir
    
    ### Starting generation of VHDL Test Bench
    ### Generating input stimulus
    ### Done generating input stimulus; length 3429 samples.
    ### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\basicfir_tb.vhd
    ### Please wait ...
    ### Done generating VHDL Test Bench
    >> 

    As the messages indicate, the coder creates the folder hdlsrc under your current working folder and places the files basicfir.vhd and basicfir_tb.vhd in that folder.

    Observe that the messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the MATLAB Editor.

    The generated VHDL code has the following characteristics:

    • VHDL entity named basicfir.

    • Registers that use asynchronous resets when the reset signal is active high (1).

    • Ports have the following names:

      VHDL Port	Name
      Input	data_in
      Output	data_out
      Clock input	clk
      Clock enable input	clk_enable
      Reset input	reset

    • An extra register for handling filter output.

    • Clock input, clock enable input and reset ports are of type STD_LOGIC and data input and output ports are of type STD_LOGIC_VECTOR.

    • Coefficients are named coeffn, where n is the coefficient number, starting with 1.

    • Type safe representation is used when zeros are concatenated: '0' & '0'...

    • Registers are generated with the statement ELSIF clk'event AND clk='1' THEN rather than with the rising_edge function.

    • The postfix string _process is appended to process names.

    The generated test bench:

    • Is a portable VHDL file.

    • Forces clock, clock enable, and reset input signals.

    • Forces the clock enable input signal to active high.

    • Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.

    • Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.

    • Applies a hold time of 2 nanoseconds to data input signals.

    • Applies impulse, step, ramp, chirp, and white noise stimulus types.

14. When you have finished generating code, click Close to close the Generate HDL dialog box.

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Getting Familiar with the Basic FIR Filter's Generated VHDL Code

Get familiar with the filter's generated VHDL code by opening and browsing through the file basicfir.vhd in an ASCII or HDL simulator editor:

1. Open the generated VHDL filter file basicfir.vhd.

2. Search for basicfir. This line identifies the VHDL module, using the string you specified for the Name option in the Target pane. See step 5 in Configuring and Generating the Basic FIR Filter's VHDL Code.

3. Search for Tutorial. This is where the coder places the text you entered for the Comment in header option. See step 10 in Configuring and Generating the Basic FIR Filter's VHDL Code.

4. Search for HDL Code. This section lists coder options you modified in Configuring and Generating the FIR Filter's Optimized Verilog Code.

5. Search for Filter Settings. This section describes the filter design and quantization settings as you specified in Designing a Basic FIR Filter in FDATool and Quantizing the Basic FIR Filter.

6. Search for ENTITY. This line names the VHDL entity, using the string you specified for the Name option in the Target pane. See step 5 in Configuring and Generating the Basic FIR Filter's VHDL Code.

7. Search for PORT. This PORT declaration defines the filter's clock, clock enable, reset, and data input and output ports. The ports for clock, clock enable, and reset signals are named with default strings. The ports for data input and output are named with the strings you specified for the Input port and Output port options on the Ports tab of the Generate HDLdialog box. See step 12 in Configuring and Generating the Basic FIR Filter's VHDL Code.

8. Search for Constants. This is where the coefficients are defined. They are named using the default naming scheme,coeffn, where n is the coefficient number, starting with 1.

9. Search for Signals. This is where the filter's signals are defined.

10. Search for process. The PROCESS block name Delay_Pipeline_process includes the default PROCESS block postfix string _process.

11. Search for IF reset. This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the PROCESS block applies the default asynchronous reset style when generating VHDL code for registers.

12. Search for ELSIF. This is where the VHDL code checks for rising edges when the filter operates on registers. The default ELSIF clk'event statement is used instead of the optional rising_edge function.

13. Search for Output_Register. This is where filter output is written to an output register. Code for this register is generated by default. In step 13 in Configuring and Generating the Basic FIR Filter's VHDL Code, you cleared the Add input register option, but left the Add output register selected. Also note that the PROCESS block name Output_Register_process includes the default PROCESS block postfix string _process.

14. Search for data_out. This is where the filter writes its output data.

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Verifying the Basic FIR Filter's Generated VHDL Code

This section explains how to verify the basic FIR filter's generated VHDL code with the generated VHDL test bench. Although this tutorial uses the Mentor Graphics^® ModelSim^® software as the tool for compiling and simulating the VHDL code, you can use any VHDL simulation tool package.

To verify the filter code, complete the following steps:

1. Start your simulator. When you start the Mentor Graphics ModelSim simulator, a screen display similar to the following appears.

   

2. Set the current folder to the folder that contains your generated VHDL files. For example:

   cd c:/hdlfilter_tutorials/hdlsrc
   

3. If necessary, create a design library to store the compiled VHDL entities, packages, architectures, and configurations. In the Mentor Graphics ModelSim simulator, you can create a design library with the vlib command.

   vlib work
   

4. Compile the generated filter and test bench VHDL files. In the Mentor Graphics ModelSim simulator, you compile VHDL code with the vcom command. The following commands compile the filter and filter test bench VHDL code.

   vcom basicfir.vhd
   vcom basicfir_tb.vhd
   

   The following screen display shows this command sequence and informational messages displayed during compilation.

   

5. Load the test bench for simulation. The procedure for doing this varies depending on the simulator you are using. In the Mentor Graphics ModelSim simulator, you load the test bench for simulation with the vsim command. For example:

   vsim work.basicfir_tb
   

   The following figure shows the results of loading work.basicfir_tb with the vsim command.

   

6. Open a display window for monitoring the simulation as the test bench runs. For example, in the Mentor Graphics ModelSim simulator, you can use the following command to open a wave window to view the results of the simulation as HDL waveforms:

   add wave *
   

   The following wave window displays.

   

7. To start running the simulation, issue the appropriate command for your simulator. For example, in the Mentor Graphics ModelSim simulator, you can start a simulation with the run command.

   The following display shows the run -all command being used to start a simulation.

   

   As your test bench simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the HDL code generation options you selected. You must determine whether the results are expected based on the customizations you specified when generating the filter VHDL code.

   Note   The failure message that appears in the preceding display is not flagging an actual error. If the message includes the string Test Complete, the test bench has successfully run to completion. The Failure part of the message is tied to the mechanism that the coder uses to end the simulation.

   The following wave window shows the simulation results as HDL waveforms.

   

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Creating a Folder for Your Tutorial Files

Optimized FIR Filter Tutorial

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