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IIR Filter Tutorial

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Designing an IIR Filter in FDATool Quantizing the IIR Filter Configuring and Generating the IIR Filter's VHDL Code Getting Familiar with the IIR Filter's Generated VHDL Code Verifying the IIR Filter's Generated VHDL Code

Designing an IIR Filter in FDATool

This tutorial guides you through the steps for designing an IIR filter, generating Verilog code for the filter, and verifying the Verilog code with a generated test bench.

This section guides you through the procedure of designing and creating a filter for an IIR filter. This section assumes you are familiar with the MATLAB user interface and the Filter Design & Analysis Tool (FDATool).

1. Start the MATLAB software.

2. Set your current folder to the folder you created in Creating a Folder for Your Tutorial Files.

3. Start the FDATool by entering the fdatool command in the MATLAB Command Window. The Filter Design & Analysis Tool dialog box appears.

   

4. In the Filter Design & Analysis Tool dialog box, set the following filter options:

   Option	Value
   Response Type	Highpass
   Design Method	IIR Butterworth
   Filter Order	Specify order:5
   Frequency Specifications	Units: Hz Fs: 48000 Fc: 10800

5. Click Design Filter. The FDATool creates a filter for the specified design. The following message appears in the FDATool status bar when the task is complete.

   Designing Filter... Done

   For more information on designing filters with the FDATool, see Using FDATool with Filter Design Toolbox Software in the Filter Design Toolbox documentation.

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Quantizing the IIR Filter

You should quantize filters for HDL code generation. To quantize your filter,

1. Open the IIR filter design you created in Designing an IIR Filter in FDATool if it is not already open.

2. Click the Set Quantization Parameters button in the left-side toolbar. The FDATool displays the Filter arithmetic list in the bottom half of its dialog box.

   

3. Select Fixed-point from the list. The FDATool displays the first of three tabbed panels of its dialog box.

   

   You use the quantization options to test the effects of various settings with a goal of optimizing the quantized filter's performance and accuracy.

4. Select the Filter Internals tab and set Rounding mode to Floor and Overflow Mode to Saturate.

5. Click Apply. The quantized filter appears as follows.

   

For more information on quantizing filters with the FDATool, see Using FDATool with Filter Design Toolbox Software in the Filter Design Toolbox documentation.

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Configuring and Generating the IIR Filter's VHDL Code

After you quantize your filter, you are ready to configure coder options and generate the filter's VHDL code. This section guides you through the procedure for starting the Filter Design HDL Coder GUI, setting some options, and generating the VHDL code and a test bench for the IIR filter you designed and quantized in Designing an IIR Filter in FDATool and Quantizing the IIR Filter:

1. Start the Filter Design HDL Coder GUI by selecting Targets > Generate HDL in the FDATool dialog box. The FDATool displays the Generate HDL dialog box.

   

2. In the Name text box of the Target pane, type iir. This option names the VHDL entity and the file that will contain the filter's VHDL code.

3. In the Comment in header text box, type Tutorial - IIR Filter. The coder adds the comment to the end of the header comment block in each generated file.

   

4. Select the Ports tab. The Ports pane appears.

   

5. Clear the check box for the Add output register option. The Ports pane should now appear as in the following figure.

   

6. Select the Advanced tab. The Advanced pane appears.

   

7. Select the Use 'rising_edge' for registers option. The Advanced pane should now appear as in the following figure.

   

8. Click on the Test bench tab in the Generate HDL dialog box. In the File name text box, replace the default name with iir_tb. This option names the generated test bench file.

   

9. In the Generate HDL dialog box, click Generate to start the code generation process. When code generation completes, click OK to close the dialog box.

   The coder displays the following messages in the MATLAB Command Window as it generates the filter and test bench VHDL files:

   ### Starting VHDL code generation process for filter: iir
   ### Starting VHDL code generation process for filter: iir
   ### Generating: c:\hdlfilter_tutorials\hdlsrc\iir.vhd
   ### Starting generation of iir VHDL entity
   ### Starting generation of iir VHDL architecture
   ### Second-order section, # 1
   ### Second-order section, # 2
   ### First-order section, # 3
   ### HDL latency is 2 samples
   ### Successful completion of VHDL code generation process for filter: iir
   
   ### Starting generation of VHDL Test Bench
   ### Generating input stimulus
   ### Done generating input stimulus; length 3289 samples.
   ### Generating Test bench: c:\hdlfilter_tutorials\hdlsrc\iir_tb.vhd
   ### Please wait ...
   ### Done generating VHDL Test Bench

   As the messages indicate, the coder creates the folder hdlsrc under your current working folder and places the files iir.vhd and iir_tb.vhd in that folder.

   Observe that the messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the MATLAB Editor.

   The generated VHDL code has the following characteristics:

   • VHDL entity named iir.

   • Registers that use asynchronous resets when the reset signal is active high (1).

   • Ports have the following default names:

     VHDL Port	Name
     Input	filter_in
     Output	filter_out
     Clock input	clk
     Clock enable input	clk_enable
     Reset input	reset

   • An extra register for handling filter input.

   • Clock input, clock enable input and reset ports are of type STD_LOGIC and data input and output ports are of type STD_LOGIC_VECTOR.

   • Coefficients are named coeffn, where n is the coefficient number, starting with 1.

   • Type safe representation is used when zeros are concatenated: '0' & '0'...

   • Registers are generated with the rising_edge function rather than the statement ELSIF clk'event AND clk='1' THEN.

   • The postfix string _process is appended to process names.

   The generated test bench:

   • Is a portable VHDL file.

   • Forces clock, clock enable, and reset input signals.

   • Forces the clock enable input signal to active high.

   • Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.

   • Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.

   • Applies a hold time of 2 nanoseconds to data input signals.

   • Applies step, ramp, and chirp stimulus types.

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Getting Familiar with the IIR Filter's Generated VHDL Code

Get familiar with the filter's generated VHDL code by opening and browsing through the file iir.vhd in an ASCII or HDL simulator editor:

1. Open the generated VHDL filter file iir.vhd.

2. Search for iir. This line identifies the VHDL module, using the string you specified for the Name option in the Target pane. See step 2 in Configuring and Generating the IIR Filter's VHDL Code.

3. Search for Tutorial. This is where the coder places the text you entered for the Comment in header option. See step 5 in Configuring and Generating the IIR Filter's VHDL Code.

4. Search for HDL Code. This section lists coder options you modified inConfiguring and Generating the IIR Filter's VHDL Code.

5. Search for Filter Settings. This section of the VHDL code describes the filter design and quantization settings as you specified in Designing an IIR Filter in FDATool and Quantizing the IIR Filter.

6. Search for ENTITY. This line names the VHDL entity, using the string you specified for the Name option in the Target pane. See step 2 in Configuring and Generating the IIR Filter's VHDL Code.

7. Search for PORT. This PORT declaration defines the filter's clock, clock enable, reset, and data input and output ports. The ports for clock, clock enable, reset, and data input and output signals are named with default strings.

8. Search for CONSTANT. This is where the coefficients are defined. They are named using the default naming scheme, coeff_xm_sectionn, where x is a or b, m is the coefficient number, and n is the section number.

9. Search for SIGNAL. This is where the filter's signals are defined.

10. Search for input_reg_process. The PROCESS block name input_reg_process includes the default PROCESS block postfix string _process. This is where filter input is read from an input register. Code for this register is generated by default. In step 7 in Configuring and Generating the Basic FIR Filter's VHDL Code, you cleared the Add output register option, but left the Add input register option selected.

11. Search for IF reset. This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the PROCESS block applies the default asynchronous reset style when generating VHDL code for registers.

12. Search for ELSIF. This is where the VHDL code checks for rising edges when the filter operates on registers. The rising_edge function is used as you specified in the Advanced pane of the Generate HDLdialog box. See step 10 in Configuring and Generating the IIR Filter's VHDL Code.

13. Search for Section 1. This is where second-order section 1 data is filtered. Similar sections of VHDL code apply to another second-order section and a first-order section.

14. Search for filter_out. This is where the filter writes its output data.

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Verifying the IIR Filter's Generated VHDL Code

This sections explains how to verify the IIR filter's generated VHDL code with the generated VHDL test bench. Although this tutorial uses the Filter Design Toolbox simulator as the tool for compiling and simulating the VHDL code, you can use any HDL simulation tool package.

To verify the filter code, complete the following steps:

1. Start your simulator. When you start the Filter Design Toolbox simulator, a screen display similar to the following appears.

   

2. Set the current folder to the folder that contains your generated VHDL files. For example:

   cd hdlsrc

3. If necessary, create a design library to store the compiled VHDL entities, packages, architectures, and configurations. In the Filter Design Toolbox simulator, you can create a design library with the vlib command.

   vlib work

4. Compile the generated filter and test bench VHDL files. In the Filter Design Toolbox simulator, you compile VHDL code with the vcom command. The following the commands compile the filter and filter test bench VHDL code.

   vcom iir.vhd
   vcom iir_tb.vhd

   The following screen display shows this command sequence and informational messages displayed during compilation.

   

5. Load the test bench for simulation. The procedure for doing this varies depending on the simulator you are using. In the Filter Design Toolbox simulator, you load the test bench for simulation with the vsim command. For example:

   vsim work.iir_tb

   The following display shows the results of loading work.iir_tb with the vsim command.

   

6. Open a display window for monitoring the simulation as the test bench runs. For example, in the Filter Design Toolbox simulator, you can use the following command to open a wave window to view the results of the simulation as HDL waveforms.

   add wave *
   

   The following wave window displays.

   

7. To start running the simulation, issue the appropriate command for your simulator. For example, in the Filter Design Toolbox simulator, you can start a simulation with the run command.

   The following display shows the run -all command being used to start a simulation.

   

   As your test bench simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the HDL code generation options you selected. You must determine whether the results are expected based on the customizations you specified when generating the filter VHDL code.

   Note   The warning messages that note Time: 0 ns in the preceding display are not errors and you can ignore them. The failure message that appears in the preceding display is not flagging an error. If the message includes the string Test Complete, the test bench has successfully run to completion. The Failure part of the message is tied to the mechanism that the coder uses to end the simulation.

   The following wave window shows the simulation results as HDL waveforms.

   

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Optimized FIR Filter Tutorial

Generating HDL Code for a Filter Design

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