Filter Design HDL Coder™

AddInputRegister

Generate extra register in HDL code for filter input

Settings

'on' (default)

Add an extra input register to the filter's generated HDL code.

The code declares a signal named input_register and includes a PROCESS block similar to the block below. Names and meanings of the timing parameters (clock, clock enable, and reset) and the coding style that checks for clock events may vary depending on other property settings.

Input_Register_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    input_register <= (OTHERS => '0');
  ELSIF clk'event AND clk = '1' THEN
    IF clk_enable = '1' THEN
      input_register <= input_typeconvert;
    END IF;
  END IF;
END PROCESS Input_Register_Process ;

'off'

Omit the extra input register from the filter's generated HDL code.

Consider omitting the extra register if you are incorporating the filter into HDL code that already has a source for driving the filter. You might also consider omitting the extra register if the latency it introduces to the filter is not tolerable.

See Also

AddOutputRegister

Properties — Alphabetical List

AddOutputRegister