Filter Design HDL Coder™

Optimizing Final Summation for FIR Filters

If you are generating HDL code for an FIR filter, consider optimizing the final summation technique to be applied to the filter. By default, the coder applies linear adder summation, which is the final summation technique discussed in most DSP text books. Alternatively, you can instruct the coder to apply tree or pipeline final summation. When set to tree mode, the coder creates a final adder that performs pair-wise addition on successive products that execute in parallel, rather than sequentially. Pipeline mode produces results similar to tree mode with the addition of a stage of pipeline registers after processing each level of the tree.

In comparison,

• The number of adder operations for linear and tree mode are the same, but the timing for tree mode might be significantly better due to summations occurring in parallel.

• Pipeline mode optimizes the clock rate, but increases the filter latency by the base 2 logarithm of the number of products to be added, rounded up to the nearest integer.

• Linear mode ensures numeric accuracy in comparison to the original filter object. Tree and pipeline modes can produce numeric results that differ from those produced by the filter object.

To change the final summation to be applied to an FIR filter,

1. Select one of the following options in the Filter settings pane of the Generate HDL dialog box:

   For...	Select...
   Linear mode (the default)	Linear from the FIR adder style menu
   Tree mode	Tree from the FIR adder style menu
   Pipeline mode	The Add pipeline registers check box

2. If you specify tree or pipelined mode, consider setting an error margin for the generated test bench to account for numeric differences. The error margin is the number of least significant bits the test bench will ignore when comparing the results. To set an error margin,

   1. Click More Test Bench Settings in the Test bench settings pane of the Generate HDL dialog box. The More Test Bench Settings dialog box appears.

   2. Specify an integer in the Error margin (bits) field that indicates an acceptable minimum number of bits by which the numeric results can differ before the coder issues a warning.

   3. Click Apply to register the change or OK to register the change and close the dialog box.

3. Continue setting other options or click Generate to initiate code generation.

Command Line Alternative: Use the generatehdl and generatetb functions with the property FIRAdderStyle or AddPipelineRegisters to optimize the final summation for FIR filters.

Optimizing Coefficient Multipliers

Speed vs. Area Optimizations for FIR Filters