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Speed vs. Area Optimizations for FIR Filters

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Overview of Speed vs. Area Optimizations Parallel and Serial Architectures Specifying Speed vs. Area Tradeoffs via generatehdl Properties Selecting Parallel and Serial Architectures in the Generate HDL Dialog Box

Overview of Speed vs. Area Optimizations

The coder provides options that extend your control over speed vs. area tradeoffs in the realization of FIR filter designs. To achieve the desired tradeoff, you can either specify a fully parallel architecture for generated HDL filter code, or choose one of several serial architectures. Supported architectures are described in Parallel and Serial Architectures.

The full range of parallel and serial architecture options is supported by properties passed in to the generatehdl command, as described in Specifying Speed vs. Area Tradeoffs via generatehdl Properties.

Alternatively, you can use the Architecture pop-up menu on the Generate HDL dialog box to choose parallel and serial architecture options, as described in Selecting Parallel and Serial Architectures in the Generate HDL Dialog Box.

The following table summarizes the filter types that are available for parallel and serial architecture choices.

Architecture	Available for Filter Types...
Fully parallel (default)	All filter types that are supported for HDL code generation
Fully serial	dfilt.dffir dfilt.dfsymfir dfilt.dfasymfir mfilt.firdecim mfilt.firinterp
Partly serial	dfilt.dffir dfilt.dfsymfir dfilt.dfasymfir
Cascade serial	dfilt.dffir dfilt.dfsymfir dfilt.dfasymfir

Note   The coder also supports distributed arithmetic (DA), another highly efficient architecture for realizing FIR filters. See Distributed Arithmetic for FIR Filters for information about how to use this architecture.)

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Parallel and Serial Architectures

Fully Parallel Architecture

This is the default option. A fully parallel architecture uses a dedicated multiplier and adder for each filter tap; all taps execute in parallel. A fully parallel architecture is optimal for speed. However, it requires more multipliers and adders than a serial architecture, and therefore consumes more chip area.

Serial Architectures

Serial architectures reuse hardware resources in time, saving chip area. The coder provides a range of serial architecture options, summarized below. All of these architectures have a latency of one clock period (see Latency in Serial Architectures).

The available serial architecture options are

• Fully serial: A fully serial architecture conserves area by reusing multiplier and adder resources sequentially. For example, a four-tap filter design would use a single multiplier and adder, executing a multiply/accumulate operation once for each tap. The multiply/accumulate section of the design runs at four times the filter's input/output sample rate. This saves area at the cost of some speed loss and higher power consumption.

  In a fully serial architecture, the system clock runs at a much higher rate than the sample rate of the filter. Thus, for a given filter design, the maximum speed achievable by a fully serial architecture will be less than that of a parallel architecture.

• Partly serial: Partly serial architectures cover the full range of speed vs. area tradeoffs that lie between fully parallel and fully serial architectures.

  In a partly serial architecture, the filter taps are grouped into a number of serial partitions. The taps within each partition execute serially, but the partitions execute in parallel with respect to one another. The outputs of the partitions are summed at the final output.

  When you select a partly serial architecture, you specify the number of partitions and the length (number of taps) of each partition. For example, you could specify a four-tap filter with two partitions, each having two taps. The system clock would run at twice the filter's sample rate.

• Cascade-serial: A cascade-serial architecture closely resembles a partly serial architecture. As in a partly serial architecture, the filter taps are grouped into a number of serial partitions that execute in parallel with respect to one another. However, the accumulated output of each partition is cascaded to the accumulator of the previous partition. The output of all partitions is therefore computed at the accumulator of the first partition. This technique is termed accumulator reuse. No final adder is required, which saves area.

  The cascade-serial architecture requires an extra cycle of the system clock to complete the final summation to the output. Therefore, the frequency of the system clock must be increased slightly with respect to the clock used in a noncascade partly serial architecture.

  To generate a cascade-serial architecture, you specify a partly serial architecture with accumulator reuse enabled (see Specifying Speed vs. Area Tradeoffs via generatehdl Properties. If you do not specify the serial partitions, the coder automatically selects an optimal partitioning.

Latency in Serial Architectures

Serialization of a filter increases the total latency of the design by one clock cycle. The serial architectures use an accumulator (an adder with a register) to sequentially add the products. An additional final register is used to store the summed result of all the serial partitions. An extra clock cycle is required for the operation.

Holding Input Data in a Valid State

In serial filters, data can be delivered to the outputs N cycles (N >= 2) later than the inputs. You can use the Hold input data between samples test bench option (or the HoldInputDataBetweenSamples CLI property) to determine how long (in terms of clock cycles) input data values are held in a valid state, as follows:

• When Hold input data between samples is selected (the default), input data values are held in a valid state across N clock cycles.

• When Hold input data between samples is cleared, data values are held in a valid state for only one clock cycle. For the nextN-1 cycles, data is in an unknown state (expressed as 'X') until the next input sample is clocked in.

The following figure shows the Test Bench pane of the Generate HDL dialog box with Hold input data between samples set to its default setting.

See also HoldInputDataBetweenSamples.

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Specifying Speed vs. Area Tradeoffs via generatehdl Properties

By default, generatehdl generates filter code using a fully parallel architecture. If you want to generate FIR filter code with a fully parallel architecture, you do not need to specify this explicitly.

Two properties are provided to specify serial architecture options when generating code via generatehdl:

• 'SerialPartition': This property specifies the serial partitioning of the filter.

• 'ReuseAccum': This property enables or disables accumulator reuse.

The table below summarizes how to set these properties to generate the desired architecture. The table is followed by several examples.

To Generate This Architecture...	Set SerialPartition to...	Set ReuseAccum to...
Fully parallel	Omit this property	Omit this property
Fully serial	N, where N is the length of the filter	Not specified, or 'off'
Partly serial	[p1 p2 p3...pN] : a vector of integers having N elements, where N is the number of serial partitions. Each element of the vector specifies the length of the corresponding partition. The sum of the vector elements must be equal to the length of the filter. When you define the partitioning for a partly serial architecture, consider the following: We recommend that the filter length should be divided as uniformly as possible into a vector of length equal to the number of multipliers intended. For example, if your design requires a filter of length 9 with 2 multipliers, the recommended partition is [5 4]. If your design requires 3 multipliers, the recommended partition is[3 3 3] rather than some less uniform division such as [1 4 4] or [3 4 2]. If your design is constrained by the need to compute each output value (corresponding to each input value) in an exact number N of clock cycles, use N as the largest partition size and partition the other elements as uniformly as possible. For example, if the filter length is 9 and your design requires exactly 4 cycles to compute the output, define the partition as [4 3 2]. This partition executes in 4 clock cycles, at the cost of 3 multipliers.	'off'
Cascade-serial with explicitly specified partitioning	[p1 p2 p3...pN]: a vector of integers having N elements, where N is the number of serial partitions. Each element of the vector specifies the length of the corresponding partition. The sum of the vector elements must be equal to the length of the filter. The values of the vector elements must be in descending order, except that the last two element must be equal. For example, for a filter of length 9, partitions such as[5 4] or [4 3 2] would be legal, but the partitions [3 3 3] or [3 2 4] would raise an error at code generation time.	'on'
Cascade-serial with automatically optimized partitioning	Omit this property	'on'

Specifying Parallel and Serial FIR Architectures in generatehdl

The following examples show the use of the 'SerialPartition' and 'ResuseAccum' properties in generating code with the generatehdl function. All examples assume that a direct-form FIR filter has been created in the workspace as follows:

Hd = design(fdesign.lowpass('N,Fc',8,.4));
Hd.arithmetic = 'fixed';

In this example, a fully parallel architecture is generated (by default).

generatehdl(Hd, 'Name','FullyParallel');
### Starting VHDL code generation process for filter: FullyParallel
### Generating: D:\Work\test\hdlsrc\FullyParallel.vhd
### Starting generation of FullyParallel VHDL entity
### Starting generation of FullyParallel VHDL architecture
### HDL latency is 2 samples
### Successful completion of VHDL code generation process for filter: FullyParallel

In this example, a fully serial architecture is generated. Notice that the system clock rate is nine times the filter's sample rate. Also, the HDL latency reported is one sample greater than in the previous (parallel) example.

generatehdl(Hd,'SerialPartition',9, 'Name','FullySerial')
### Starting VHDL code generation process for filter: FullySerial
### Generating: D:\Work\test\hdlsrc\FullySerial.vhd
### Starting generation of FullySerial VHDL entity
### Starting generation of FullySerial VHDL architecture
### Clock rate is 9 times the input sample rate for this architecture.
### HDL latency is 3 samples
### Successful completion of VHDL code generation process for filter: FullySerial

In this example, a partly serial architecture with three equal partitions is generated.

generatehdl(Hd,'SerialPartition',[3 3 3], 'Name', 'PartlySerial')
### Starting VHDL code generation process for filter: PartlySerial
### Generating: D:\Work\test\hdlsrc\PartlySerial.vhd
### Starting generation of PartlySerial VHDL entity
### Starting generation of PartlySerial VHDL architecture
### Clock rate is 3 times the input sample rate for this architecture.
### HDL latency is 2 samples
### Successful completion of VHDL code generation process for filter: PartlySerial

In this example, a cascade-serial architecture with three partitions is generated. The partitions are entered in descending order of size. Note that the clock rate is higher than that in the previous (partly serial without accumulator reuse) example.

generatehdl(Hd,'SerialPartition',[4 3 2], 'ReuseAccum', 'on','Name','CascadeSerial')
### Starting VHDL code generation process for filter: CascadeSerial
### Generating: D:\Work\test\hdlsrc\CascadeSerial.vhd
### Starting generation of CascadeSerial VHDL entity
### Starting generation of CascadeSerial VHDL architecture
### Clock rate is 5 times the input sample rate for this architecture.
### HDL latency is 3 samples
### Successful completion of VHDL code generation process for filter: CascadeSerial

In this example, a cascade-serial architecture is generated, with the partitioning automatically determined by the coder .

generatehdl(Hd,'ReuseAccum','on', 'Name','CascadeSerial')
### Starting VHDL code generation process for filter: CascadeSerial
### Generating: D:\Work\test\hdlsrc\CascadeSerial.vhd
### Starting generation of CascadeSerial VHDL entity
### Starting generation of CascadeSerial VHDL architecture
### Clock rate is 5 times the input sample rate for this architecture.
### Serial partition # 1 has 4 inputs.
### Serial partition # 2 has 3 inputs.
### Serial partition # 3 has 2 inputs.
### HDL latency is 3 samples
### Successful completion of VHDL code generation process for filter: CascadeSerial

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Selecting Parallel and Serial Architectures in the Generate HDL Dialog Box

The Architecture pop-up menu, located on the Generate HDL dialog box, lets you select parallel and serial architecture options corresponding to those described in Parallel and Serial Architectures. These options are

• Fully parallel (default)

• Fully serial: Nonpartitioned serial architecture, without accumulator reuse

• Partly serial: Partitioned serial architecture, without accumulator reuse (See Specifying Partitions for Partly Serial and Cascade Serial Architectures.)

• Cascade serial: Partitioned serial architecture, with accumulator reuse (See Specifying Partitions for Partly Serial and Cascade Serial Architectures.)

Note   The Architecture pop-up menu also includes the Distributed arithmetic (DA) option (see Distributed Arithmetic for FIR Filters).

The following figure shows the default (Fully parallel) architecture setting. .

Specifying Partitions for Partly Serial and Cascade Serial Architectures

When you select the Partly serial or Cascade serial option, the Generate HDL dialog box displays the Serial Partition field (shown in the following figure).

The Serial Partition field lets you enter a vector of integers specifying the number and size of the partitions, as described in Specifying Speed vs. Area Tradeoffs via generatehdl Properties.

By default, Serial Partition divides the filter into two partitions. For example, the preceding figure shows the default partition (5 4) for a filter with 9 taps.

Interactions Between Architecture Options and Other HDL Options

Selection of some Architecture menu options may change or disable other options, as described below.

• When the Fully serial option is selected, the following options are set to their default values and disabled:

  • Coefficient multipliers

  • Add pipeline registers

  • FIR adder style

• When the Partly serial option is selected:

  • The Coefficient multipliers option is set to its default value and disabled.

  • If the filter is multirate, the Clock inputs options is set to Single and disabled.

• When the Cascade serial option is selected, the following options are set to their default values and disabled:

  • Coefficient multipliers

  • Add pipeline registers

  • FIR adder style

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Optimizing Final Summation for FIR Filters

Distributed Arithmetic for FIR Filters

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