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Defaults for Script Generation Properties for Controlling Script Generation Controlling Script Generation with the EDA Tool Scripts Dialog Box |
The coder supports generation of script files for third-party Electronic Design Automation (EDA) tools. These scripts let you compile and simulate generated HDL code and/or synthesize generated HDL code.
Using the defaults, you can automatically generate scripts for the following tools:
Mentor Graphics® ModelSim® SE/PE HDL simulator
The Synplify® family of synthesis tools
By default, script generation takes place automatically, as part of the code and test bench generation process.
All script files are generated in the target directory.
When HDL code is generated for a filter Hd, the coder writes the following script files:
Hd_compile.do: Mentor Graphics ModelSim compilation script. This script contains commands to compile the generated filter code, but not to simulate it.
Hd_synplify.tcl: Synplify synthesis script
When test bench code is generated for a filter Hd, the coder writes the following script files:
Hd_tb_compile.do: Mentor Graphics ModelSim compilation script. This script contains commands to compile the generated filter and test bench code.
Hd_tb_sim.do: Mentor Graphics ModelSim simulation script. This script contains commands to run a simulation of the generated filter and test bench code.
You can enable or disable script generation and customize the names and content of generated script files using either of the following methods:
Use the generatehdl or generatetb functions, and pass in the appropriate property name/property value arguments, as described in Properties for Controlling Script Generation.
Set script generation options in the EDA Tool Scripts dialog box, as described in Controlling Script Generation with the EDA Tool Scripts Dialog Box.
A generated EDA script consists of three sections, which are generated and executed in the following order:
An initialization (Init) phase. The Init phase performs any required setup actions, such as creating a design library or a project file. Some arguments to the Init phase are implicit, for example, the top-level entity or module name.
A command-per-file phase (Cmd). This phase of the script is called iteratively, once per generated HDL file or once per signal. On each call, a different file or signal name is passed in.
A termination phase (Term). This is the final execution phase of the script. One application of this phase is to execute a simulation of HDL code that was compiled in the Cmd phase. The Term phase takes no arguments.
The coder generates scripts by passing format strings to the fprintf function. Using the GUI options (or generatehdl and generatetb properties) summarized in the following sections, you can pass in customized format strings to the script generator. Some of these format strings take arguments, such as the top-level entity or module name, or the names of the VHDL or Verilog files in the design.
You can use any legal fprintf formatting characters. For example, '\n'inserts a newline into the script file.
This section describes how to set properties in the generatehdl or generatetb functions to enable or disable script generation and customize the names and content of generated script files.
The EDAScriptGeneration property controls the generation of script files. By default, EDAScriptGeneration is set 'on'. To disable script generation, set EDAScriptGeneration to 'off', as in the following example.
generatehdl(Hd,'EDAScriptGeneration','off')
When HDL code is generated, the code generator forms script names by appending a postfix string to the filter name Hd.
When test bench code is generated, the code generator forms script names by appending a postfix string to the test bench name testbench_tb.
The postfix string depends on the type of script (compilation, simulation, or synthesis) being generated. The default postfix strings are shown in the following table. For each type of script, you can define your own postfix using the associated property.
| Script type | Property | Default Value |
|---|---|---|
| Compilation | 'HDLCompileFilePostfix' | '_compile.do' |
| Simulation | 'HDLSimFilePostfix' | '_sim.do' |
| Synthesis | 'HDLSynthFilePostfix' | '_synplify.tcl' |
The following command generates VHDL code for the filter object myfilt, specifying a custom postfix string for the compilation script. The name of the generated compilation script will be myfilt_test_compilation.do.
generatehdl(myfilt, 'HDLCompileFilePostfix', '_test_compilation.do')
Using the property name/property value pairs summarized in the following table, you can pass in customized format strings to generatehdl or generatetb. The properties are named according to the following conventions:
Properties that apply to the initialization (Init) phase are identified by the substring Init in the property name.
Properties that apply to the command-per-file phase (Cmd) are identified by the substring Cmd in the property name.
Properties that apply to the termination (Term) phase are identified by the substring Term in the property name.
| Property Name and Default | Description |
|---|---|
Name: 'HDLCompileInit' Default:'vlib work\n' | Format string passed to fprintf to write the Init section of the compilation script. |
Name: 'HDLCompileVHDLCmd' Default: 'vcom %s %s\n' | Format string passed to fprintf to write the Cmd section of the compilation script for VHDL files. The two arguments are the contents of the 'SimulatorFlags' property and the filename of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). |
Name: 'HDLCompileVerilogCmd' Default: 'vlog %s %s\n' | Format string passed to fprintf to write the Cmd section of the compilation script for Verilog files. The two arguments are the contents of the 'SimulatorFlags' property and the filename of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). |
Name:'HDLCompileTerm' Default:'' | Format string passed to fprintf to write the termination portion of the compilation script. |
Name: 'HDLSimInit' Default: ['onbreak resume\n',... 'onerror resume\n'] | Format string passed to fprintf to write the initialization section of the simulation script. |
Name: 'HDLSimCmd' Default: 'vsim work.%s\n' | Format string passed to fprintf to write the simulation command. The implicit argument is the top-level module or entity name. |
Name: 'HDLSimViewWaveCmd' Default: 'add wave sim:%s\n' | Format string passed to fprintf to write the simulation script waveform viewing command. The top-level module or entity signal names are implicit arguments. |
Name: 'HDLSimTerm' Default: 'run -all\n' | Format string passed to fprintf to write the Term portion of the simulation script |
Name: 'HDLSynthInit' Default: 'project -new %s.prj\n' | Format string passed to fprintf to write the Init section of the synthesis script. The default string is a synthesis project creation command. The implicit argument is the top-level module or entity name. |
Name: 'HDLSynthCmd' Default: 'add_file %s\n' | Format string passed to fprintf to write the Cmd section of the synthesis script. The argument is the filename of the entity or module. |
Name: 'HDLSynthTerm' Default: ['set_option -technology VIRTEX4\n',... 'set_option -part XC4VSX35\n',... 'set_option -synthesis_onoff_pragma 0\n',... 'set_option -frequency auto\n',... 'project -run synthesis\n'] | Format string passed to fprintf to write the Term section of the synthesis script. |
The following example specifies a Mentor Graphics ModelSim command for the Init phase of a compilation script for VHDL code generated from the filter myfilt.
generatehdl(myfilt, 'HDLCompileInit', 'vlib mydesignlib\n')
The following code shows the resultant script, myfilt_compile.do.
vlib mydesignlib vcom myfilt.vhd
The EDA Tool Scripts dialog box, a subdialog of the Generate HDL dialog box, lets you set all options that control generation of script files. These options correspond to the properties described in Properties for Controlling Script Generation.
To view and set options in the EDA Tool Scripts dialog box:
Open the Generate HDL dialog box.
Click the EDA Tool Scripts button (highlighted in the following figure) in the Generate HDL dialog box.
The EDA Tool scripts dialog box opens with the Compilation script options group selected, as shown in the following figure.
The Generate EDA scripts option controls the generation of script files. By default, this option is selected.
If you want to disable script generation, deselect this option and click Apply.
The list on the left of the dialog box lets you select from several categories of options. Select a category and set the options as desired. The categories are
Compilation script: options related to customizing scripts for compilation of generated VHDL or Verilog code. See Compilation Script Options for further information.
Simulation script: options related to customizing scripts for HDL simulators. See Simulation Script Options for further information.
Synthesis script: options related to customizing scripts for synthesis tools. See Synthesis Script Options for further information.
The following figure shows the Compilation script pane, with all options set to their default values.
The following table summarizes the Compilation script options.
| Option and Default | Description |
|---|---|
Compile file postfix '_compile.do' | Postfix string appended to the filter name or test bench name to form the script file name. |
Name: Compile initialization Default:'vlib work\n' | Format string passed to fprintf to write the Init section of the compilation script. |
Name: Compile command for VHDL Default: 'vcom %s %s\n' | Format string passed to fprintf to write the Cmd section of the compilation script for VHDL files. The two arguments are the contents of the Simulator flags option and the filename of the current entity or module. To omit the flags, set Simulator flags to '' (the default). |
Name: Compile command for Verilog Default: 'vlog %s %s\n' | Format string passed to fprintf to write the Cmd section of the compilation script for Verilog files. The two arguments are the contents of the Simulator flags option and the filename of the current entity or module. To omit the flags, set Simulator flags to '' (the default). |
Name:Compile termination Default:'' | Format string passed to fprintf to write the termination portion of the compilation script. |
The following figure shows the Simulation script pane, with all options set to their default values.
The following table summarizes the Simulation script options.
| Option and Default | Description |
|---|---|
Simulation file postfix '_sim.do' | Postfix string appended to the filter name or test bench name to form the script file name. |
Simulation initialization Default: ['onbreak resume\n',... 'onerror resume\n'] | Format string passed to fprintf to write the initialization section of the simulation script. |
Simulation command Default: 'vsim work.%s\n' | Format string passed to fprintf to write the simulation command. The implicit argument is the top-level module or entity name. |
Simulation waveform viewing command Default: 'add wave sim:%s\n' | Format string passed to fprintf to write the simulation script waveform viewing command. The top-level module or entity signal names are implicit arguments. |
Simulation termination Default: 'run -all\n' | Format string passed to fprintf to write the Term portion of the simulation script |
The following figure shows the Synthesis script pane, with all options set to their default values.
The following table summarizes the Synthesis script options.
| Option Name and Default | Description |
|---|---|
Name: Synthesis initialization Default: 'project -new %s.prj\n' | Format string passed to fprintf to write the Init section of the synthesis script. The default string is a synthesis project creation command. The implicit argument is the top-level module or entity name. |
Name: Synthesis command Default: 'add_file %s\n' | Format string passed to fprintf to write the Cmd section of the synthesis script. The argument is the filename of the entity or module. |
Name: Synthesis termination Default: ['set_option -technology VIRTEX4\n',... 'set_option -part XC4VSX35\n',... 'set_option -synthesis_onoff_pragma 0\n',... 'set_option -frequency auto\n',... 'project -run synthesis\n'] | Format string passed to fprintf to write the Term section of the synthesis script. |
The coder allows most combinations of filter and test bench languages. For example, it is possible to generate VHDL filter code and a Verilog test bench file, as in the following commands:
generatehdl(myfilt, 'TargetLanguage', 'VHDL') generatetb(myfilt, 'Verilog')
The following listing shows the generated test bench compilation script for the above case (myfilt_tb_compile.do). The script contains the correct language-specific compile command for the generated filter and test bench code.
vlib work vcom myfilt.vhd vlog myfilt_tb.v
The two simulation compile Cmd properties ('HDLCompileVHDLCmd', 'HDLCompileVerilogCmd') allow you to customize the compilation command for each supported target language.
You can specify generation of both VHDL and Verilog test bench code, via the Generate HDL dialog box. In this case, the test bench compilation script defaults to the Verilog compilation command.
Generation of .do test bench files, which is controlled by the ModelSim .do file option, is independent from the generation of script files.
| Generating the HDL Code | Optimizing Generated HDL Code | |
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