Filter Design HDL Coder™

ClockEnableOutputPort

For multirate filters (with single clock), specify name of clock enable output port

Settings

'string'

The default name for the generated clock enable output port isce_out.

Usage Notes

For multirate filters, a clock enable output is generated when Single is selected from the Clock inputs menu in the Generate HDL dialog. In this case only, the Clock enable output port option is enabled.

See Also

ClockInputs

ClockEnableInputPort

ClockHighTime