Filter Design HDL Coder™ClockEnableOutputPort   ClockInputPort
  

ClockHighTime

Specify period, in nanoseconds, during which test bench drives clock input signals high (1)

Settings

ns

The default is 5.

Usage Notes

The coder ignores this property if ForceClock is set to 'off'.

See Also

ClockLowTime, ForceClock, ForceClockEnable, ForceReset, HoldTime

  

ClockEnableOutputPortClockEnableOutputPort ClockInputPortClockInputPort

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