Filter Design HDL Coder™

ClockInputPort

Name HDL port for filter's clock input signals

Settings

'string'

The default clock input port name is clk.

For example, if you specify the string 'filter_clock' for filter entity Hd, the generated entity declaration might look as follows:

ENTITY Hd IS
   PORT( filter_clock   :  IN  std_logic;
         clk_enable     :  IN  std_logic;
         reset          :  IN  std_logic;
         filter_in      :  IN  std_logic_vector (15 DOWNTO 0); -- sfix16_En15
         filter_out     :  OUT std_logic_vector (15 DOWNTO 0); -- sfix16_En15
         );
ENDHd;
 

If you specify a string that is a VHDL reserved word, a reserved word postfix string is appended to form a valid VHDL identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix in for more information.

See Also

ClockEnableInputPort, InputPort, InputType, OutputPort, OutputType, ResetInputPort

ClockHighTime

ClockInputs