Filter Design HDL Coder™

ClockInputs

For multirate filters, specify generation of single or multiple clock inputs

Settings

'Single' (default)

Generate a single clock input for a multirate filter. When this option is selected, the ENTITY declaration for the filter defines a single clock input with an associated clock enable input and clock enable output. The generated code maintains a counter that controls the timing of data transfers to the filter output (for decimation filters) or input (for interpolation filters). The counter is, in effect, a secondary clock whose rate is determined by the filter's decimation or interpolation factor.

'Multiple'

Generate multiple clock inputs for a multirate filter. When this option is selected, the ENTITY declaration for the filter defines separate clock inputs (each with an associated clock enable input) for each rate of a multirate filter. (For currently supported multirate filters, there are two such rates).

Usage Notes

The Clock inputs menu is enabled only when a multirate filter (of one of the types supported for code generation) has been designed in fdatool.

The generated code assumes that the clocks are driven at the appropriate rates. You are responsible for ensuring that the clocks run at the correct relative rates for the filter's decimation or interpolation factor. To see an example, generate test bench code for your multirate filter and examine the clk_gen processes for each clock.

See Also

ClockEnableOutputPort

ClockInputPort

ClockLowTime