| Filter Design HDL Coder™ | ![]() |
Specify string to append to duplicate VHDL entity or Verilog module names
'string'
The specified postfix resolves duplicate VHDL entity or Verilog module names. The default string is _entity.
For example, if the coder detects two entities with the name MyFilt, the coder names the first entity MyFilt and the second instance MyFilt_entity.
ClockProcessPostfix, CoeffPrefix, PackagePostfix, ReservedWordPostfix
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