Filter Design HDL Coder™

FIRAdderStyle

Specify final summation technique used for FIR filters

Settings

'linear' (default)

Apply linear adder summation. This technique is discussed in most DSP text books.

'tree'

Increase clock speed while maintaining the area used. This option creates a final adder that performs pair-wise addition on successive products that execute in parallel, rather than sequentially.

Usage Notes

If you are generating HDL code for a FIR filter, consider optimizing the final summation technique by applying tree or pipeline final summation techniques. Pipeline mode produces results similar to tree mode with the addition of a stage of pipeline registers after processing each level of the tree.

For information on applying pipeline mode, see AddPipelineRegisters.

Consider the following tradeoffs when selecting the final summation technique for your filter:

• The number of adder operations for linear and tree mode are the same, but the timing for tree mode might be significantly better due to summations occurring in parallel.

• Pipeline mode optimizes the clock rate, but increases the filter latency by the base 2 logarithm of the number of products to be added, rounded up to the nearest integer.

• Linear mode ensures numeric accuracy in comparison to the original filter function. Tree and pipeline modes can produce numeric results that differ from those produced by the original filter function.

See Also

AddPipelineRegisters, CoeffMultipliers, OptimizeForHDL

ErrorMargin

ForceClock