Filter Design HDL Coder™

ForceClock

Specify whether test bench forces clock input signals

Settings

'on' (default)

Specify that the test bench forces the clock input signals. When this option is set, the clock high and low time settings control the clock waveform.

'off'

Specify that a user-defined external source forces the clock input signals.

See Also

ClockHighTime, ClockLowTime, ForceClockEnable, ForceReset, HoldTime,

FIRAdderStyle

ForceClockEnable