Filter Design HDL Coder™

ForceClockEnable

Specify whether test bench forces clock enable input signals

Settings

'on' (default)

Specify that the test bench forces the clock enable input signals to active high (1) or active low (0), depending on the setting of the clock enable input value.

'off'

Specify that a user-defined external source forces the clock enable input signals.

See Also

ClockHighTime, ClockLowTime, ForceClock, ForceReset, HoldTime,

ForceClock

ForceReset