Filter Design HDL Coder™

ForceReset

Specify whether test bench forces reset input signals

Settings

'on' (default)

Specify that the test bench forces the reset input signals. If you enable this option, you can also specify a hold time to control the timing of a reset.

'off'

Specify that a user-defined external source forces the reset input signals.

See Also

ClockHighTime, ClockLowTime, ForceClock, ForceClockEnable, HoldTime,

ForceClockEnable

FracDelayPort