Filter Design HDL Coder™

HoldInputDataBetweenSamples - Specify how long input data values are held in valid state

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This property can be applied to filters that do not have fully parallel implementations. (See Parallel and Serial Architectures and Distributed Arithmetic for FIR Filters).

In such filter implementations, data can be delivered to the outputs N cycles (N >= 2) later than the inputs. The HoldInputDataBetweenSamples property determines how long (in terms of clock cycles) input data values for these signals are held in a valid state, as follows:

When HoldInputDataBetweenSamples is set 'on' (the default), input data values are held in a valid state across N clock cycles.
When HoldInputDataBetweenSamples is set 'off' , data values are held in a valid state for only one clock cycle. For the nextN-1 cycles, data is in an unknown state (expressed as 'X') until the next input sample is clocked in.

HoldInputDataBetweenSamples - Specify how long input data values are held in valid state

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