Filter Design HDL Coder™

HoldTime

Specify hold time for filter data input signals and forced reset input signals

Settings

ns

Specify the number of nanoseconds (a positive integer) during which filter data input signals and forced reset input signals are held past the clock rising edge. The default is 2.

This option applies to reset input signals only if forced resets are enabled.

Usage Notes

The hold time is the amount of time that reset input signals and input data are held past the clock rising edge. The following figures show the application of a hold time (t_hold) for reset and data input signals when the signals are forced to active high and active low.

Note   A reset signal is always asserted for two cycles plus thold.

Hold Time for Reset Input Signals

Hold Time for Data Input Signals

See Also

ClockHighTime, ClockLowTime, ForceClock, ForceClockEnable, ForceReset

HoldInputDataBetweenSamples

InlineConfigurations