Filter Design HDL Coder™

InputPort

Name HDL port for filter's input signals

Settings

'string'

The default string is filter_in.

For example, if you specify the string 'filter_data_in' for filter entity Hd, the generated entity declaration might look as follows:

ENTITY Hd IS
   PORT( clk               :  IN  std_logic;
         clk_enable        :  IN  std_logic;
         reset             :  IN  std_logic;
         filter_data_in    :  IN  std_logic_vector (15 DOWNTO 0); 
         filter_out        :  OUT std_logic_vector (15 DOWNTO 0); 
         );
END Hd;

If you specify a string that is a VHDL reserved word, a reserved word postfix string is appended to form a valid VHDL identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix for more information.

See Also

ClockEnableInputPort, ClockInputPort, OutputPort, OutputType, ResetInputPort

InlineConfigurations

InputType