MultifileTestBench

Divide generated test bench into helper functions, data, and HDL test bench code files

Settings

'on'

Write separate files for test bench code, helper functions, and test bench data. The file names are derived from the test bench name and the TestBenchDataPostfix property as follows:

TestBenchName_TestBenchDataPostfix

For example, if the filter name is test_fir, and the target language is VHDL, the default test bench file names are:

If the filter name is test_fir and the target language is Verilog, the default test bench file names are:

'off' (default)

Write a single test bench file containing all HDL test bench code and helper functions and test bench data.

See Also

TestBenchName, TestBenchDataPostFix

  


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