Learn more about Filter Design HDL Coder

ResetAssertedLevel

Specify asserted (active) level of reset input signal

Settings

'active-high' (default)

Specify that the reset input signal must be driven high (1) to reset registers in the filter design. For example, the following code fragment checks whether reset is active high before populating the delay_pipeline register:

Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
.
.
.

'active-low'

Specify that the reset input signal must be driven low (0) to reset registers in the filter design. For example, the following code fragment checks whether reset is active low before populating the delay_pipeline register:

Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '0' THEN
    delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
.
.
.

ResetAssertedLevel

Settings

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