Version 1.4 (R2006a) Filter Design HDL Coder™ Software Release Notes

Version 1.4 (R2006a) Filter Design HDL Coder™ Software

This table summarizes what's new in V1.4 (R2006a):

New features and changes introduced in this version are

• Speed vs. Area Tradeoff Options for FIR Filters

• Code Generation Support for Delay Filter

• Rounding Behavior in Generated HDL Code

Speed vs. Area Tradeoff Options for FIR Filters

The coder now provides options that extend your control over speed vs. area tradeoffs in the realization of single-rate direct-form FIR filter designs.

This release note summarizes the new options. See Speed vs. Area Optimizations for FIR Filters in the Filter Design HDL Coder User's Guide for full details and examples. Further examples are given in the HDL Serial Architectures for FIR Filters demo (hdlserialfir.m).

To achieve the desired speed vs. area tradeoff, you can either specify a fully parallel architecture for generated HDL filter code, or choose one of several serial architectures. The following architectures are supported:

• Fully parallel: This is the default option. A fully parallel architecture uses a dedicated multiplier and adder for each filter tap; all taps execute in parallel. A fully parallel architecture is optimal for speed. However, it requires more multipliers and adders than a serial architecture, and therefore consumes more chip area.

• Fully serial: A fully serial architecture conserves area by reusing multiplier and adder resources sequentially. For example, a four-tap filter design would use a single multiplier and adder, executing a multiply/accumulate once for each tap. The multiply/accumulate section of the design runs at four times the filter's input/output sample rate. This saves area at the cost of some speed loss and higher power consumption.

• Partly serial: Partly serial architectures cover the full range of speed vs. area tradeoffs that lie between the two extreme cases, fully parallel and fully serial architectures.

  In a partly serial architecture, the filter taps are grouped into a number of serial partitions. The taps within each partition execute serially, but the partitions execute in parallel with respect to one another. The outputs of the partitions are summed at the final output.

• Cascade-serial: A cascade-serial architecture closely resembles a partly serial architecture. As in a partly serial architecture, the filter taps are grouped into a number of serial partitions that execute in parallel with respect to one another. However, the accumulated output of each partition is cascaded to the accumulator of the previous partition. The output of all partitions is therefore computed at the accumulator of the first partition. This technique is termed accumulator reuse. No final adder is required, which saves area.

The full range of parallel/serial architecture options is supported by new properties passed in to the generatehdl command.

Alternatively, you can use the new Architecture option on the HDL Options dialog box (see the following figure) to choose between the basic Fully Parallel or Fully Serial architectures.

The new options are supported for the following filter types:

• dfilt.dffir

• dfilt.dfsymfir

• dfilt.dfasymfir

Code Generation Support for Delay Filter

The coder now supports code generation for the Delay filter type (dfilt.delay). See the Signal Processing Toolbox™ documentation for information on this filter type.

The Delay filter is often used in a cascade with other filter types. See Generating Code for Cascade Filters Filter Design HDL Coder User's Guide for general considerations on using cascade filters in code generation.

Rounding Behavior in Generated HDL Code

In Release 2006a, filter objects (and fixed-point arithmetic in general) support a fixed-point rounding mode (Round) that behaves identically to the MATLAB^® round function. However, the coder does not support this rounding behavior in generated HDL code. When generating code from a filter that has the RoundMode property set to Round, The coder uses Nearest rounding mode instead. A warning is issued when code generation is initiated, as shown in the following example.

b = [0.05 0.9 0.05];
Hd = dfilt.dffir(b);
Hd.arithmetic = 'fixed';
Hd.FilterInternals = 'SpecifyPrecision';
Hd.RoundMode = 'Round';
generatehdl(Hd);
Warning: RoundMode 'round' is not supported for HDL generation. Using 'nearest' instead.
.
.
.
### Successful completion of VHDL code generation process for filter: Hd

If you are generating code from a fixed-point filter created in FDATool, this situation does not occur because the FDATool Round towards menu does not include the Round option.

Compatibility Considerations

Before generating HDL code from your existing filter objects, check the RoundMode property and if it is set to Round, use another mode to avoid the warning.

Version 1.5 (R2006b) Filter Design HDL Coder™ Software

Version 1.3 (R14SP3) Filter Design HDL Coder™ Software