Version 1.5 (R2006b) Filter Design HDL Coder™ Software Release Notes

Version 1.5 (R2006b) Filter Design HDL Coder Software

This table summarizes what's new in Version 1.5 (R2006b).

New features and changes introduced in this version are

• Distributed Arithmetic Support for FIR Filters

• Multirate Support for Fully Serial Architectures

• Generate HDL Dialog Box Supports All Parallel and Serial Architecture Options

• Enhanced Code Generation for Symmetric Multirate FIR Filters

• EDAScriptGeneration Property Added

• ResetValue Property Merged with ResetAssertedLevel Property

• Clock EnableValue for Test Benches Always Active-High

Distributed Arithmetic Support for FIR Filters

The coder now supports Distributed Arithmetic (DA) in HDL code generated for several single-rate and multirate FIR filter structures. DA is a widely-used technique for implementing sum of products computations without use of multipliers. Designers frequently use DA to build efficient Multiply-Accumulate Circuitry (MAC) for filters and other DSP applications.

DA code generation is supported for fixed-point realizations of the following FIR filter structures:

• dfilt.dffir

• dfilt.dfsymfir

• dfilt.dfasymfir

• mfilt.firdecim

• mfilt.firinterp

You can enable and control DA code generation using generatehdl properties provided for that purpose, or by selecting the Distributed Arithmetic (DA) option from the Architecture pop-up menu in the Generate HDL dialog box (shown in the following figure).

See Distributed Arithmetic for FIR Filters in the Filter Design HDL Coder documentation for a complete description of DA related options and properties.

Multirate Support for Fully Serial Architectures

The coder adds support for generation of fully serial architectures for the following multirate filter types:

• mfilt.firdecim

• mfilt.firinterp

The following table summarizes the filter types that are available for parallel and serial architecture choices. See Speed vs. Area Optimizations for FIR Filters in the Filter Design HDL Coder User's Guide for a full description of these options.

Generate HDL Dialog Box Supports All Parallel and Serial Architecture Options

Previously, the Architecture pop-up menu on the HDL Options dialog box provided a choice between two basic (Fully parallel or Fully serial) architectures. Other architecture options were available only by setting generatehdl properties (ReuseAccum and SerialPartition).

The Generate HDL dialog box now supports the full range of architecture options. As shown in the following figure, the Architecture pop-up menu now includes Partly serial and Cascade serial options.

When the Partly serial or Cascade serial option is selected, the Generate HDL dialog box displays the Serial Partition field (shown in the following figure). See Speed vs. Area Optimizations for FIR Filters in the Filter Design HDL Coder User's Guide for a full description of serial and parallel architecture options.

Note   The Architecture pop-up menu also includes the new Distributed arithmetic (DA) option (see Distributed Arithmetic Support for FIR Filters).

Enhanced Code Generation for Symmetric Multirate FIR Filters

In this release, the coder enhances code generation for Direct-Form FIR Polyphase Decimator (mfilt.firdecim) filters by using the symmetry in polyphase coefficients for each FIR subfilter. The code generator inserts adders before multipliers to sum the input samples that correspond to the symmetric taps.

EDAScriptGeneration Property Added

The EDAScriptGeneration property controls the generation of script files. By default, EDAScriptGeneration is set 'on'. To disable script generation, set EDAScriptGeneration to 'off', as in the following example:

generatehdl(Hd,'EDAScriptGeneration','off') 

See Generating Scripts for EDA Tools in the Filter Design HDL Coder User's Guide for further information.

ResetValue Property Merged with ResetAssertedLevel Property

In previous releases, the ResetValue property (or the Reset value option in the Test Bench Options dialog box) allowed test bench reset input signal levels (active-high or active-low) to be set independently from the level specified for resets in the generated filter code.

In this release, the ResetValue property has been merged with the ResetAssertedLevel property (Reset asserted level menu in the HDL filter pane of the Generate HDL dialog box). The Reset asserted level setting determines the rest level for both filter and test bench reset input signals, ensuring consistency among reset signals.

Compatibility Considerations

If you have existing M-file scripts or saved FDATool settings that rely on setting the ResetValue property independently of ResetAssertedLevel, you should change them to use only ResetAssertedLevel.

Clock EnableValue for Test Benches Always Active-High

The clock enable value for test benches is now always active-high. The ClockEnableValue property and the corresponding Clock enable value option in the Test Bench Options dialog box have been removed. Setting an active-low clock enable value for test benches is no longer supported.

Compatibility Considerations

You should remove any code that sets or references the ClockEnableValue property from your existing M-file scripts.

Version 2.0 (R2007a) Filter Design HDL Coder Software

Version 1.4 (R2006a) Filter Design HDL Coder Software