| Version 2.2 (R2008a) Filter Design HDL Coder™ Software Release Notes | |
This table summarizes what's new in Version 2.2 (R2008a).
| New Features and Changes | Version Compatibility Considerations | Fixed Bugs and Known Problems | Related Documentation at Web Site |
|---|---|---|---|
| Yes Details below | Yes—Details labeled as Compatibility Considerations, below. See also Summary. | No | Printable Release Notes: PDF |
New features and changes introduced in this version are:
Code Generation Support for Multirate Farrow Sample Rate Converter Filters
GUI Support for Storage of FIR Filter Coefficients in RAM or Register File
generatetb Supports Default Specification of Test Bench Type
The coder now supports HDL code generation for multirate Farrow sample rate converter (mfilt.farrowsrc) filters.
The coder also supports code generation for cascades that include a mfilt.farrowsrc filter, provided that the mfilt.farrowsrc filter is in the last position of the cascade.
See Generating Code for Multirate Farrow Sample Rate Converters for further information.
You can now direct the coder to generate separate files for test bench code, helper functions, and test bench data using the following command–line properties:
MultifileTestBench: This property lets you divide the generated test bench into separate files containing helper functions, data, and HDL test bench code. See MultifileTestBench for details.
TestbenchDataPostfix: This property lets you specify a suffix added to the test bench data file name when generating a multi-file test bench. See TestBenchDataPostFix for details.
The following command-line properties are supported in the current release:
HoldInputDataBetweenSamples: You can apply this property to filters that do not have parallel architectures. In such filters, data can be delivered to the outputs N cycles (N >= 2) later than the inputs. The HoldInputDataBetweenSamples property determines how long (in terms of clock cycles) input data values for these signals are held in a valid state. See HoldInputDataBetweenSamples for details.
TestBenchReferencePostFix: This property lets you specify a string appended to the names of reference signals generated in test bench code. See TestBenchReferencePostFix for details.
For direct-form FIR filters, the coder now provides two GUI options that let you generate a RAM or register file interface for loading coefficients, and test the interface. These options correspond to the CoefficientSource and TestbenchCoeffStimulus properties, introduced in the previous release.
The new GUI options are:
The Coefficient source menu on the Generate HDL dialog box (shown in the following figure) lets you select whether coefficients are obtained from the filter object and hard-coded (Internal), or from a generated RAM interface (Processor interface) The corresponding command-line property is CoefficientSource.
The Coefficient stimulus option on the More Test Bench Settings dialog box lets you specify how the test bench tests the generated RAM or register file interface. The corresponding command-line property is TestbenchCoeffStimulus.
For detailed information on these options, see Specifying Storage of FIR Filter Coefficients in RAM or Register File in the Filter Design HDL Coder User's Guide.
In previous releases, the generatetb function required an explicit argument specifying the test bench type.
In the current release, you can optionally omit the test bench type argument. In this case, the test bench type defaults to the current setting of the TargetLanguage property ('VHDL' or 'Verilog'). The TargetLanguage property is set by the most recent execution of the generatehdl command.
In the following example, TargetLanguage is set to 'Verilog' by the generatehdl command. Then, generatetb generates a Verilog test bench, by default.
>> generatehdl(my_filter,'TargetLanguage','Verilog') ### Starting Verilog code generation process for filter: my_filter ### Starting Verilog code generation process for filter: my_filter ### Generating: H:\hdlsrc\my_filter.v ### Starting generation of my_filter Verilog module ### Starting generation of my_filter Verilog module body ### HDL latency is 2 samples ### Successful completion of Verilog code generation process for filter: my_filter >> generatetb(my_filter, 'TestBenchName', 'MyFilterTB_V') ### Starting generation of VERILOG Test Bench ### Generating input stimulus ### Done generating input stimulus; length 3312 samples. ### Generating Test bench: H:\hdlsrc\MyFilterTB_V.v ### Please wait ....... ### Done generating VERILOG Test Bench
See also generatetb.
For more information about the process of removing functions and properties, see "About Functions and Properties Being Removed" in What's in the Release Notes.
| Function or Property Name | What Happens When You Use Function or Property? | Use This Instead | Compatibility Considerations |
|---|---|---|---|
| 'Modelsim' test bench type argument for generatetb function | Warns | No replacement | See ModelSim .do Test Bench Option Deprecated. |
| ScaleWarnBits property | Property is ignored | No replacement | See ScaleWarnBits Property No Longer Supported. |
The Modelsim .do file test bench generation option, and the corresponding'Modelsim' test bench type argument for the generatetb function, are deprecated in the current release and will not be supported in future releases.
In the current release, the coder displays a warning during test bench generation if this option is specified.
If your scripts use the 'Modelsim' test bench type argument for the generatetb function, you should remove the 'Modelsim' argument. The test bench type will then take a default value as described in generatetb Supports Default Specification of Test Bench Type.
See also generatetb.
The ScaleWarnBits property is no longer supported. The corresponding GUI option, Minimum overlap of scale values (bits) , has been removed from the Advanced pane of the More HDL Settings dialog box.
If you have M-files that contain commands that reference the ScaleWarnBits property, such references are ignored. Remove references to ScaleWarnBits from your code.
This section summarizes revisions and enhancements that have been made to the Filter Design HDL Coder™ GUI.
The Generate HDL dialog box now includes the Coefficient source menu. See GUI Support for Storage of FIR Filter Coefficients in RAM or Register File .
The More Test Bench Settings dialog box now includes the Coefficient stimulus option. See GUI Support for Storage of FIR Filter Coefficients in RAM or Register File .
The Minimum overlap of scale values (bits) option has been removed from the Advanced pane of the More HDL Settings dialog box. (See ScaleWarnBits Property No Longer Supported.) The following figure shows the default settings for the Advanced pane.
| Filter Design HDL Coder™ Release Notes | Version 2.1 (R2007b) Filter Design HDL Coder™ Software | |
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