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Version 2.3 (R2008b) Filter Design HDL Coder Software

This table summarizes what's new in Version 2.3 (R2008b).

New Features and Changes	Version Compatibility Considerations	Fixed Bugs and Known Problems	Related Documentation at Web Site
Yes Details below	Yes—Details labeled as Compatibility Considerations, below. See also Summary.	No	No

New features and changes introduced in this version are:

• Test Bench Enhancements

• Distributed Arithmetic Restriction Removed for Symmetrical and Asymmetrical FIR Filters

• -novopt Flag Added to the Default Simulation Command in Generated Compilation Scripts

• ModelSim .do Test Bench Option Removed

Test Bench Enhancements

The appearance of the More Test Bench Settings dialog box has been revised, and a number of options have been added. The following figure shows the default set of options in the More Test Bench Settings dialog box. Options that have been added to the GUI are highlighted.

Each new option (except Setup time (ns)) has a corresponding command-line property. The following table lists the new options and their corresponding command-line properties, and provides hyperlinks to the relevant documentation.

GUI Option	Command-Line Property
Setup time (ns): See Setting a Hold Time for Data Input Signals and Configuring Resets.	This display-only field does not have a corresponding user-settable command-line property.
Clock enable delay (in clock cycles): See Configuring the Clock.	TestBenchClockEnableDelay
Reset length: See Configuring Resets.	ResetLength
Hold input data between samples: See Holding Input Data in a Valid State.	HoldInputDataBetweenSamples
Initialize test bench inputs: See Setting an Initial Value for Test Bench Inputs.	InitializeTestBenchInputs
Multi-file test bench: See Splitting Test Bench Code and Data into Separate Files.	MultifileTestBench
Test bench data file name postfix: See Splitting Test Bench Code and Data into Separate Files.	TestBenchDataPostFix
Test bench reference postfix: See Setting a Postfix for Reference Signal Names.	TestBenchReferencePostFix
Generate cosimulation blocks: See Generating HDL Cosimulation Blocks for Use with HDL Simulators.	GenerateCoSimBlock

Distributed Arithmetic Restriction Removed for Symmetrical and Asymmetrical FIR Filters

The DARadix property specifies the number of bits processed simultaneously in a distributed arithmetic architecture. In previous releases, when generating code for symmetrical (dfilt.dfsymfir) or asymmetrical (dfilt.dfasymfir) FIR filters, the DARadix value was required to be less than or equal to 2. Specification of a DARadix value greater than 2 for these filter types caused a warning to be issued during code generation.

In Release 2008b, the coder permits use of DARadix values greater than 2 for these filter types. Other requirements for setting the DARadix property still apply. For details, see DARadix Property and Considerations for Symmetrical and Asymmetrical Filters in the Filter Design HDL Coder documentation.

For general information on distributed arithmetic support, see Distributed Arithmetic for FIR Filters in the Filter Design HDL Coder documentation.

-novopt Flag Added to the Default Simulation Command in Generated Compilation Scripts

For improved operation with the ModelSim^® (Version 6.2 and later) simulator, the default values of the HDLSimCmd property string (and the Simulation Command GUI option) now includes the -novopt flag, as follows:

'vsim -novopt work.%s\n'

The -novopt flag directs the ModelSim simulator not to perform optimizations that remove signals from the simulation view.

Compatibility Considerations

If you are using ModelSim 6.0 or an earlier version, you should set the HDLSimCmd property string (or the Simulation Command GUI option) to omit the -novopt option, as follows:

'vsim work.%s\n'

ModelSim .do Test Bench Option Removed

The Modelsim .do file test bench generation option, and the corresponding'Modelsim' test bench type argument for the generatetb function, are no longer supported and have been removed from the current release.

In the current release, generatetb displays an error message and terminates test bench generation if the 'Modelsim' test bench type option is specified.

Compatibility Considerations

If your scripts use the 'Modelsim' test bench type argument for the generatetb function, you should remove the 'Modelsim' argument. The test bench type will then default to the current setting of the TargetLanguage property ('VHDL' or 'Verilog').

See also generatetb.

Version 2.4 (R2009a) Filter Design HDL Coder Software

Version 2.2 (R2008a) Filter Design HDL Coder Software

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