| Filter Design HDL Coder™ | |
Specify number and size of partitions generated for serial FIR filter architectures
N
Generate a fully serial architecture for a filter of length N.
[p1 p2 p3...pN]
Where [p1 p2 p3...pN] is a vector of N integers, generate a partly serial architecture with N partitions. Each element of the vector specifies the length of the corresponding partition. The sum of the vector elements must be equal to the length of the filter.
To save chip area in a partly serial architecture, you can enable the ReuseAccum property.
See Speed vs. Area Optimizations for FIR Filters for a complete description of parallel and serial architectures and a list of filter types supported for each architecture.
| SafeZeroConcat | SimulatorFlags | |
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