Filter Design HDL Coder™

UseRisingEdge

Specify VHDL coding style used to check for rising edges when operating on registers

Settings

'on'

Use the VHDL rising_edge function to check for rising edges when operating on registers. The generated code applies rising_edge as shown in the following PROCESS block:

Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
  ELSIF rising_edge(clk) THEN
    IF clk_enable = '1' THEN
      delay_pipeline(0) <= signed(filter_in);
		delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS Delay_Pipeline_Process ;

'off' (default)

Check for clock events when operating on registers. The generated code checks for a clock event as shown in the ELSIF statement of the following PROCESS block:

Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
  ELSIF clk'event AND clk = '1' THEN
    IF clk_enable = '1' THEN
      delay_pipeline(0) <= signed(filter_in);
		delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS Delay_Pipeline_Process ;

Usage Notes

The two coding styles have different simulation behavior when the clock transitions from 'X' to '1'.

See Also

CastBeforeSum, InlineConfigurations, , LoopUnrolling, SafeZeroConcat, UseAggregatesForConst, UseRisingEdge

UserComment

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