| Embedded IDE Link™ MU | |
MPC5500 Support in Embedded IDE Link MU
Create interrupt service routines (ISR) in the software generated by the build process. When you incorporate this block in your model, code generation results in ISRs on the processor that either run the processes that are downstream from this block or trigger an Idle Task block connected to this block. Core interrupts trigger the ISRs. System interrupts trigger the core interrupts.
Specify a vector of interrupt numbers for the interrupts to install. The block services these interrupts. When your model or code raises one of these interrupts, either through hardware or software, this block reacts to the interrupt and runs the associated downstream block or function. The valid range or interrupts depends on the processor. For example, MPC5553 processors support 212 interrupts. MPC5554 processors support 308 interrupts. Each interrupt in the row vector must be unique. Interrupts that you do not specify in this parameter cause system failures if your project raises them.
The width of the block output signal corresponds to the number of interrupt numbers specified in this field. The values in this field and the preemption flag entries in Preemption flags: preemptible-1, non-preemptible-0 define how the code and processor handle interrupts during asynchronous scheduler operations.
Each output of the HW/SW Interrupt block drives a downstream block (for example, a function call subsystem). Simulink® task priority specifies the Simulink priority of the downstream blocks. Specify an array of priorities corresponding to the interrupt numbers entered in Core interrupt numbers. In the default settings shown in the figure, interrupts 3 and 5 have the same priority value—7.
Proper code generation requires rate transition code (see Rate Transitions and Asynchronous Blocks). The task priority values ensure absolute time integrity when the asynchronous task must obtain real time from its base rate or its caller. Typically, assign priorities for these asynchronous tasks that are higher than the priorities assigned to periodic tasks.
If multiple interrupts share the same priority and are asserted simultaneously, the block selects the lowest numbered interrupt first.
Higher-priority interrupts can preempt interrupts that have lower priority. To allow you to control preemption, use the preemption flags to specify whether an interrupt can be preempted.
Entering 1 indicates that the interrupt can be preempted.
Entering 0 indicates the interrupt cannot be preempted.
You cannot set a task that has priority higher than the base rate to be preemptable.
When Interrupt numbers contains more than one interrupt value, you can assign different preemption flags to each interrupt by entering a vector of flag values to correspond to the order of the interrupts in Interrupt numbers. If Interrupt numbers contains more than one interrupt, and you enter only one flag value in this field, that status applies to all interrupts.
In the default settings [0 1], the interrupt with priority 5 in Interrupt numbers is not preemptible and the priority 8 interrupt can be preempted.
Select this option to put the block and processor in software vector mode. Enabling this option creates a common interrupt handler. Clearing this option puts the processor in hardware vector mode. Refer to the MULTI documentation for more information about the modes.
When you select this option, Simulink adds an input port to the HW/SW Interrupt block. This port is used in simulation only. Connect one or more simulated interrupt sources to the simulation input.
| Hardware Interrupt | Idle Task | |
| © 1984-2008- The MathWorks, Inc. - Site Help - Patents - Trademarks - Privacy Policy - Preventing Piracy - RSS |