| Target Support Package™ FM5 | |
Target Support Package FM5/ MPC555 Driver Library
The MPC555 Resource Configuration block differs in function and behavior from conventional blocks. Therefore, we refer to this block as the MPC555 Resource Configuration object.
The MPC555 Resource Configuration object maintains configuration settings that apply to the MPC555 CPU and its MIOS, QADC, and TouCAN subsystems. Although the MPC555 Resource Configuration object resembles a conventional block in appearance, it is not connected to other blocks via input or output ports. This is because the purpose of the MPC555 Resource Configuration object is to provide information to other blocks in the model. MPC555 device driver blocks register their presence with the MPC555 Resource Configuration object when they are added to a model or subsystem; they can then query the MPC555 Resource Configuration object for required information.
To install a MPC555 Resource Configuration object in a model or subsystem, open the top-level Target Support Package FM5 library and select the MPC555 Resource Configuration icon. Then drag and drop it into your model or subsystem, like a conventional block.
Having installed a MPC555 Resource Configuration object into your model or subsystem, you can then select and edit configuration settings in the MPC555 Resource Configuration window. See Using the MPC555 Resource Configuration Window for further information.
Note Any model or subsystem using device driver blocks from the Target Support Package FM5 library must contain an MPC555 Resource Configuration object. You should place an MPC555 Resource Configuration object at the top level system for which you are going to generate code. If your whole model is going to run on the target processor, put the MPC555 Resource Configuration object at the root level of the model. If you are going to generate code from separate subsystems (to run specific subsystems on the target), place an MPC555 Resource Configuration object at the top level of each subsystem. You should not have more than one MPC555 Resource Configuration object in the same branch of the model hierarchy. Errors will result if these conditions are not met. |
When the MPC555 Resource Configuration block is placed into a model, it modifies the preloadfcn callback of the model. If you wish to add a command to the preloadfcn callback of a model that already has an MPC555 Resource Configuration block, do not remove the commands that are already installed.
Instead, copy the installed preloadfcn callback and append your commands. Then set the preloadfcn to the merged command. If you corrupt the preloadfcn, you can retrieve the command from any model that has an MPC555 Resource Configuration block, as the preloadfcn will be the same for all models. You can retrieve the preloadfcn with the following command:
plf = get_param(bdroot,'preloadfcn')
A configuration is a collection of parameter values affecting the operation of a group of device driver blocks in one of the Target Support Package FM5 libraries, such as the MIOS1, QADC64 or TouCAN libraries. The MPC555 Resource Configuration object currently supports the following types of configurations:
System Configuration Parameters: MPC555 clocks and other CPU-related parameters.
QADC64 Configuration Parameters: parameters related to the Queued Analog-to-Digital Converter module (QADC).
QADC64E Configuration Parameters: parameters related to the QADC for the MPC565.
MIOS1 Configuration Parameters: parameters related to the Modular Input/Output System (MIOS).
TouCAN Configuration Parameters: parameters related to the CAN 2.0B Controller Module (TouCAN).
Time Processor Unit (TPU3) Configuration Parameters: parameters related to the Time Processor Unit module.
Serial Communications Interface (SCI) Configuration Parameters: parameters related to the Serial Communications Interface.
An active configuration is a configuration associated with blocks of the model or subsystem in which the MPC555 Resource Configuration object is installed. There is always an active MPC555 configuration. For any other configuration type (e.g., QADC, MIOS, or TouCAN), there is at most one active configuration. Such configurations are only active when relevant device driver blocks are present in the model or subsystem.
Consider this model, which contains a MPC555 Resource Configuration object but no MPC555 device driver blocks.
This model has only one active configuration, for the MPC555 itself, as shown in the MPC555 Resource Configuration window.
When a device driver block is added to the model, an appropriate configuration is created and activated. The following figure shows an MIOS Digital Out block added to the model.
The addition of the MIOS Digital Out block causes an MIOS configuration to be added to the list of active configurations, as shown in this figure.
A configuration remains active until all blocks associated with it are removed from the model or subsystem. At that point, the configuration is in an inactive state. Inactive configurations are not shown in the MPC555 Resource Configuration window. You can reactivate a configuration by simply adding an appropriate block into the model.
Note When using device driver blocks from the Target Support Package FM5 libraries in conjunction with the MPC555 Resource Configuration block, do not disable or break library links on the driver blocks. If library links are disabled or broken, the MPC555 Resource Configuration block will operate incorrectly. |
To open the MPC555 Resource Configuration window, install a MPC555 Resource Configuration object in your model or subsystem, and double-click on the MPC555 Resource Configuration icon. The MPC555 Resource Configuration window then opens.
MPC555 Resource Configuration Window
This figure shows the MPC555 Resource Configuration window for a model that has active configurations for MPC555, MIOS1, QADC, and TouCAN.
The MPC555 Resource Configuration window consists of the following elements:
Active Configurations panel: This panel displays a list of currently active configurations. To edit a configuration, click on its entry in the list. The parameters for the selected configuration then appear in the System configuration panel.
To link back to the library associated with an active configuration, right-click on its entry in the list. From the pop-up menu that appears, select Go to library.
To see documentation associated with an active configuration, right-click on its entry in the list. From the popup menu that appears, select Help.
System configuration panel: This panel lets you edit the parameters of the selected configuration. The parameters of each configuration type are detailed in MPC555 Resource Configuration Window Parameters.
Status panel: The Status panel displays error messages that may arise if resource allocation conflicts are detected in the configuration.
Validate Configuration button: After you edit a configuration, you should always click the Validate Configuration button to check for resource allocation conflicts. For example, if both TouCAN modules A and B are assigned to interrupt level IRQ 1, the Validate Configuration process will detect the conflict and display a warning in the Status panel.
Note that the Validate Configuration button does not validate the entire model; it only checks for resource allocation conflicts related to the selected configuration. To detect problems related to the model as a whole, select Update diagram (Ctrl+D) from the Simulink Edit menu.
Close button: Dismisses the window.
The sections below describe the parameters for each type of configuration in the MPC555 Resource Configuration window. The default parameter settings are optimal for most purposes. If you want to change the settings, we suggest you read the sections of the MPC555 User's Manual referenced below. You can find this document at the following URL:
http://www.freescale.com/files/microcontrollers/doc/user_guide/MPC555UM.pdf
The rt_OneStep function is the basic execution driver of all programs generated by the Target Support Package FM5 product. rt_OneStep is installed as a timer interrupt service routine; it sequences calls to the model_step function. The RT_ONESTEP_IRQ_LEVEL parameter lets you associate rt_OneStep with any of the available IRQ levels (0..7). Do not select Interrupts Disabled, or the model will not work.
See the "Data Structures and Program Execution" section in the Real-Time Workshop Embedded Coder documentation for a detailed description of the rt_OneStep function.
The parameters Oscillator_Frequency, USIU_PLPRCR_B_DIVF, USIU_PLPRCR_B_MF, USIU_SCCR_B_DFNH, USIU_SCCR_B_DFNL, USIU_SCCR_B_EBDF in the MPC555 group control the speed of the main clocks in the MPC555. Refer to section 8, "Clocks and Power Control," in the MPC555 User's Manual for information on these settings.
Some pre-defined configurations may be applied by inserting the block Switch Target Hardware Configuration into your model. This block is found in the Utilities sublibrary of the MPC555 Driver Library, see Switch Target Configuration. Insert this block in your model, then double-click on the block to choose a configuration from the available list. When one of the pre-defined configurations is selected, the appropriate settings will be applied automatically.
Note the Target Support Package FM5 product only supports an Oscillator_Frequency of 4 MHz or 20 MHz; the setting of this parameter must correspond to the crystal frequency on your target hardware.
You might want to change these parameters in order to allow a different system clock value to be used; a faster system clock will increase the processing performance, as well as increasing power consumption. With default settings, the default values result in a system clock of 20 MHz for the MPC555. To gain additional processing power it may be desirable to increase the system clock. For the MPC555, the system clock may be increased up to 40 MHz. The exact settings that are required to achieve a desired system clock value may be calculated using the formulae provided in the MPC555 User Documentation. For example
System clock = Oscillator_Frequency * (MF+1) / (DIVF +1)
— where MF is the multiplying factor USIU_PLPRCR_B_MF and DIVF is the dividing factor USIU_PLPRCR_B_DIVF.
For example, if your hardware uses an external oscillator frequency of 20 MHz (e.g. as used on a phyCORE-MPC555 board), then changing the value of USIU_PLPRCR_B_MF from 0 to 1 will increase the system clock from 20 to 40 MHz. For different external oscillator frequencies or different processor variants you should consult the user documentation for your hardware.
The Queued Analog-To-Digital Converter Module 64 (QADC64) Configuration parameters configure the QADC64 operational mode and supports the blocks in the QADC sublibrary.
The QADC64 performs 10 bit analog to digital conversion on an input signal. Currently the blocks in this library support only the continuous scan mode of operation. In continuous scan mode, the QADC64 is set to run, and then continuously acquires data into its result buffer. Input is double buffered, so the model can read the result buffer at any time to get the latest available signal data.
The MPC555 has two QADC modules, QADC_A and QADC_B. You can program these individually. By default each QADC module has 16 input channels. By attaching an external multiplexer to three of the analog input pins, you can increase the number of possible channels to 41. These pins become outputs from the processor and can act as inputs to an analog multiplexer. The Multiplex Mode parameter determines whether the QADC64 operates in internally or externally multiplexed mode.
Refer to section 13, "Queued Analog-to-Digital Converter Module-64," in the MPC555 User's Manual for detailed information about the QADC64.
In general, you should not need to change any of the settings of the parameters described below from their defaults. The other parameters are advanced settings. Refer to section 13, "Queued Analog-to-Digital Converter Module-64," in the MPC555 User's Manual for information on these settings.
Configures the QADC64 for internally or externally multiplexed mode by setting the MUX bit. The MUX bit determines the interpretation of the channel numbers and forces the MA[2:0] pins to be outputs. Valid settings are
0 = Internally multiplexed : 16 possible channels
1 = Externally multiplexed : 41 possible channels
Prescaler clock high (PSH) time. The default is 7. The PSH field selects the QCLK high time in the prescaler. PSH value plus 1 represents the high time in IMB clocks.
Prescaler clock low (PSL) time. The default is 7. The PSL field selects the QCLK low time in the prescaler. PSL value plus 1 represents the low time in IMB clocks.
The Enhanced QADC functions are for MPC56x processors – you will see an error message if you try to configure these for an MPC555. Use QADC blocks for an MPC555; for an MPC56x set your target processor accordingly in the Target Preferences and then you can use the QADCE blocks.
The Enhanced Queued Analog-To-Digital Converter Module 64 (QADC64E) Configuration parameters configure the QADC64E operational mode and supports the blocks in the Enhanced QADC sublibrary.
Configures the QADC64 for internally or externally multiplexed mode by setting the MUX bit. The MUX bit determines the interpretation of the channel numbers and forces the MA[2:0] pins to be outputs. Valid settings are
0 = Internally multiplexed : 40 possible channels
1 = Externally multiplexed : 65 possible channels
Set the Q clock frequency you want here. The QCLK_Actual_Frequency field displays the true value achieved. QCLK_Actual_Frequency and QCLK_Prescalar are read only fields for information.
The MIOS counter clock is generated by the MIOS counter prescaler submodule. The MIOS counter clock drives the other MIOS1 submodules. The value shown for the counter clock is calculated automatically as the system clock frequency divided by the prescaler value.
This allows all counters on the MIOS1 to be frozen when the processor is stopped in debug mode. Note that this is in addition to the Freeze Enable setting for individual submodules on the MIOS1. To allow the counters on a particular submodule to be stopped, select Freeze enable here, and select Hold output when at debug break point (freeze enable) in the block parameters associated with the submodule (e.g., MIOS Pulse Width Modulation block or MIOS Waveform Measurement block).
These two counters provide reference clocks to submodules such as the MIOS Pulse Width Modulation Submodule and the MIOS Double Action Submodule (Frequency / Period measurement) subsystems. If you change the Clock Select to anything other than MMCSM Clock Prescaler, the MIOS Pulse Width Modulation and MIOS Waveform Measurement blocks will not work as expected. To change the clock frequency and hence the available resolution of pulse width modulation and waveform measurement, change the Clock Prescaler to a value between 0 and 255.
Refer to section 15.10, "MIOS Modulus Counter Submodule (MMCSM)," in the MPC555 User's Manual for information on these settings.
The parameters listed below are the same for TouCAN modules A and B (and C, for MPC56x). Consult Section 16 of the MPC555 User's Manual before editing the TouCAN configuration parameter defaults.
The transmit queue for each TouCAN module requires a processor interrupt to run. Select an interrupt level (0-31) that is not used by any other device. Use the Apply button to make sure you do not select an interrupt level that is already in use. Do not disable interrupts: this will stop the TouCAN Transmit block from working correctly.
Buffers 0-13 use this mask. Setting a bit to 0 in the mask causes the corresponding bits in the incoming message's identifier to be masked out (i.e., ignored).
0 – Corresponding bit in the incoming message's identifier is "don't care"
1 – Corresponding bit in the incoming message's identifier is checked against the identifier specified in the TouCAN Receive block associated with this buffer.
Same as Global RX Mask, but the mask applies only to buffer 14.
Same as Global RX Mask, but the mask applies only to buffer 15.
Specify whether the buffer masks are Standard or Extended frame IDs. If you want to receive Extended Frames in your model, you should set the Mask Type to Extended Message. The mask type option tells the compiler how to map the bits specified in the mask options to the bits in the hardware. The decision as to whether a message is a Standard or Extended frame is defined on a per message buffer basis.
Enter the desired bit rate. The default bit rate is 500000.0.
The number of TouCAN clock ticks per message bit.
The maximum number of clock ticks that the TouCAN device can resynchronize over when it detects that it is losing message synchronization.
The point in the message where the TouCAN tries to sample the value of the message bit, between 0 and 1.
You cannot select the slew rate for the TouCAN modules. By default, the slow slew rate is selected for the TouCAN modules. This results in a slew rate of 50ns for TouCAN C, and 200ns for the other modules.
Length (number of messages) of the transmit queue. The transmit queue holds messages that are waiting to be transmitted. An increase in performance can be achieved by reducing the queue length. However, if the queue's length is too small it may become full, causing messages to be lost.
Choose either Single TouCAN Buffer or Three TouCAN Buffers. This parameter is used in conjunction with all TouCAN Transmit blocks in the model for this TouCAN module that are operating in Queued transmission with shared buffer mode. If you select Single TouCAN Buffer, then all messages that are queued will be transmitted via a single hardware buffer; in this case, it is possible that a low priority message in the transmit buffer will block higher priority messages that are in the queue. To avoid this problem, use the option Three TouCAN Buffers. When three buffers are used, the driver ensures that the message entered into arbitration to be transmitted via the CAN bus is always the highest priority message available; furthermore in this mode the TouCAN module is able to transmit messages continuously by re-loading hardware buffers that become empty while another buffer is active transmitting.
The default is to Use ROM TPU Functions (0). Select Use Emulation Mode (1) to use downloaded TPU functions in DPTRAM. Use the parameters under TPU_Emulation to configure downloads for emulation mode. For an example see the demo model mpc555rt_tpu_emu. Note that CCP Program_Prepare downloads will fail because DPTRAM_AB contains TPU microcode for emulation mode.
This enables TPU interrupts. The default is disabled. If your model contains any TPU3 Programmable Time Accumulator blocks, you will need to choose an interrupt level.
Select Bank 0, 1 or 2. If you select an invalid memory bank for the TPU module (e.g. Bank 2 for TPU C) you will see an error message when you click Apply. This must match the selection for the parameters TPU_Function_Mask_Bank_0 (also Bank_1, Bank_2).
The TCR1 and TCR2 timebases are configurable for TPU Channels A, B and C.
The parameters under the TCR1 tree allow you full control to specify the clock speed of the TCR1 timebase. Consult Section 17 of the MPC555 User's Manual before editing the TPU configuration parameter defaults. The parameters listed below are the same for TPU modules A, B and C.
If you choose to use the Enhanced_Prescaler_Divide, then you can choose to divide the IMB clock down by either 2, 4, 6, 8, ... , 60, 62, 64.
Here you can choose whether you use the Standard Prescaler (set by Standard_Prescaler_Divide) or the Enhanced Prescaler (set by Enhanced_Prescaler_Divide) to derive the Prescaler Clock.
If you choose to use the Standard_Prescaler_Divide then you can choose to divide the IMB clock down by either 32 or 4.
Whichever type of prescaler you choose (standard or extended), there is a further prescaler that is applied to the clock. TCR1P_Divide divides the Prescaler Clock by 1, 2, 4, or 8. The resulting clock is the TCR1 timebase.
Read-only field displaying calculated TCR1 clock frequency.
TPUMCR2_DIV2 (the last setting under the tree) allows you to choose to use a set of prescalers to divide the IMB clock down further (Use Prescalers (0)), or to just divide the IMB clock by two (IMB Clock / 2 (1)). If you choose the divide by two option then none of the other settings are applicable and are marked N/A. Note this is the last setting purely because the parameters are laid out in alphabetical order.
The parameters under the TCR2 tree for specifying the clock speed of the TCR2 timebase are the same for TPU modules A, B and C. You can configure the TCR2 to use an external clock.
You can choose to divide the TCR2 prescaler clock down by either 1, 2, 4, or 8.
Read-only field displaying calculated TCR2 clock frequency when using the gated IMB clock. This field displays zero when using an external clock, as it cannot predict an external clock signal.
Select from Rise transition T2CLK, Gated IMB clock, Fall transition T2CLK, or Rise & fall transition T2CLK.
The Gated IMB clock setting uses the T2CLK pin to gate the internal clock as a source for TCR2 (a logical AND between the input on the T2CLK pin and the IMB clock is performed).
The other settings allow TCR2 to be clocked from the selected edge of an external clock signal applied to the T2CLK pin.
See the MPC555 User's Manual for the effects of setting the TCR2_PSCK2 bit. The default, Divide by 1, leaves the TCR2P_Divide setting the only prescaler applied to the clock (if using an external clock). If using the gated IMB clock there is always an additional implicit divide by 8.
Use these settings to configure downloads for TPU emulation mode.
Use the settings under these two parameters to configure emulation mode for TPU modules A and B (TPU_DPTRAM_AB) and/or TPU modules C (TPU_DPTRAM_C). The parameters listed below are the same for TPU modules A, B and C.
Enter the name of the S19 file containing the TPU functions to be downloaded. The specified file must be either in the current working directory OR the MATLAB path if an absolute path is not explicitly specified. Note the file name will not be accepted unless TPU_EMU_S19Download is set to Download custom code. This parameter retains a memory of the last file specified.
The S19 file must be produced from an .asc microcode mask file and a TPU microcode assembler. The TPU function names and TPU function numbers are specified in the .asc file. Make sure you enter the same TPU function names and numbers in the TPU_Function_Mask_Bank parameters.
Read only field displaying the full path to the download file. Check this to ensure the correct file is shown.
Select Download custom code to download to DPTRAM for emulation mode. The default is No code download.
Use the parameters under here to specify which TPU Function Numbers correspond to which TPU functions. For example, typing PTA for TPU_Function_D will specify that the PTA function is configured as TPU function number 13. If you enter a string that is not a valid TPU function name, when you click Apply an error message appears in the status field, followed by a list of possible TPU Function Names and their corresponding full function names. Names must be exact including case. The specified TPU function names and numbers must correspond to those specified in the TPU_EMU_Mask_File.
This read-only field shows the achieved serial interface bit rate. In general this value differs slightly from the requested bit rate, but is the closest value that can be achieved by setting allowed values in the MPC555 registers SCC1R0 and SCC2R0 for QSMCM submodules SCI1 and SCI2 respectively.
Enter the desired bit rate for serial communications in this field. Appropriate register settings will be calculated automatically. You can check the actual bit rate in the Bit_rate_achieved field.
Select either Standard transmit/receive or Loopback mode enabled. The loopback mode may be useful for test purposes where the serial interface is required to receive data that it transmitted itself.
Select the desired combination of word length and parity/no parity.
If parity is enabled, you must select Odd parity or Even parity.
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