Target Support Package™ FM5

QADCE Analog In - Input driver enables use of Queued Analog-Digital Converter (QADC64) in continuous scan mode on MPC56x (561-6)

Library

Target Support Package FM5/ MPC555 Driver Library/ Enhanced Queued Analog-To-Digital Converter Module-64

Description

The QADCE Analog In block sets the QADC64E into continuous scan mode. It then samples the specified channels at the specified rate. In continuous scan mode, the analog-to-digital converter is scanned as fast as possible, at a rate much faster than the sample rate of the model. Using continuous scan mode ensures that your application will obtain the latest signal value.

The MPC56x has two QADC64E modules, A and B. You can program these individually. You can place only one instance of the QADCE Analog In block per module in your model or subsystem.

Dialog Box

QADC module

Select module A or B.

Channels

A vector of numbers representing channels to be scanned. A channel number in the Channels vector selects the input channel number corresponding to the analog input pin to be sampled and converted.

The analog input pin channel number assignments and the pin definitions vary, depending on whether the QADC64E is operating in multiplexed or nonmultiplexed mode. The queue scan mechanism makes no distinction between an internally or externally multiplexed analog input.

In nonmultiplexed mode, specify a vector of numbers from [44..59 64..87] corresponding to pins AN44..AN59 and AN64..AN87.

See the table following for the mapping in multiplexed mode between the channel numbers and the hardware pins.

Justification

Converted data is read from the 10-bit wide QADC64E result word table into a 16-bit word. Data from the result word table can be accessed in three different formats. The Justification menu selects from the following formats:

Right-justified (unsigned): with zeros in the higher order unused bits.

Left-justified (signed): with the most significant bit inverted to form a sign bit, and zeros in the unused lower order bits. In this mode, zero is treated as the half scale of the input range.

Left-justified (unsigned): with zeros in the unused lower order bits.

Sample time

Block sample time; determines sample rate at which the port is monitored

Mapping Bits To Hardware Pins

Use the following table to work out how the block ports and bits map to processor pins on the MPC565 in multiplexed mode.

In summary

• No multiplexing:

  channels available 44-59 and 64-87

• A only multiplexing:

  channels available 0-31; 48-51; 55-59; 64-87

• B only multiplexing:

  channels available 0-31; 48-59; 64-71; 75-87

• A and B multiplexing:

  channels available 0-31; 48-51; 55-59; 64-71; 75-87

Multiplexed Scan Mode

In this table, MA0 to MA2 indicates these pins (A_ and B_PQA0-2) are used as output pins to drive an external demultiplexer.

QADC Digital In

QADCE Digital In