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CMOS OR - Model CMOS OR gate behaviorally

Library

Logic

Description

The CMOS OR block represents a CMOS OR logic gate behaviorally:

• The block output voltage value equals the High level output voltage parameter value if the logic levels of any of the gate inputs are 1.

• The block output voltage value equals the Low level output voltage parameter value otherwise.

The block determines the logic levels of the gate inputs as follows:

• If the gate voltage is greater than the threshold voltage, the block interprets the input as logic 1.

• Otherwise, the block interprets the input as logic 0.

The threshold voltage is the voltage value at midpoint between the High level input voltage parameter value and the Low level input voltage parameter value.

Note   The block does not model the internal individual MOSFET devices that make up the gate.

The block models the gate as follows:

• The gate inputs have infinite resistance and finite or zero capacitance.

• The gate output (voltage source) drives a series resistor and capacitor connected to ground.

• The block sets the value of the gate output capacitor such that the resistor-capacitor time constant equals the Propagation delay parameter value.

Basic Assumptions and Limitations

The block does not model the internal individual MOSFET devices that make up the gate. This limitation has the following implications:

• The block does not accurately model the gate's response to input noise and inputs that are around the logic threshold voltage.

• The block does not accurately model dynamic response.

• The block's linear drop in output voltage as a function of output current is an approximation to the MOSFET output behavior.

To model a logic gate at the device level, use the netlist2sl function to import the netlist of the logic gate.

Dialog Box and Parameters

Inputs Tab

Low level input voltage

Voltage value below which the block interprets the input voltage as logic LOW. The default value is 2 V.

High level input voltage

Voltage value above which the block interprets the input voltage as logic HIGH. The default value is 3 V.

Average input capacitance

Fixed capacitance that approximates the input capacitance for a MOSFET gate. The MOSFET capacitance depends on the applied voltage. When you drive this block with another gate, the Average input capacitance produces a rise time similar to that of the MOSFET. You can usually find this capacitance value on a manufacturer datasheet. The default value is 5 pF. Setting this value to zero may result in faster simulation times.

Outputs Tab

Low level output voltage

Voltage value at the output when the output logic level is LOW. The default value is 0 V.

High level output voltage

Voltage value at the output when the output logic level is HIGH. The default value is 5 V.

Output resistance

Value of the series output resistor that is used to model the drop in output voltage resulting from the output current. The default value is 450 Ω. You can derive this value from a datasheet by dividing the high-level output voltage by the maximum low-level output current.

Propagation delay

Time it takes for the output to swing from LOW to HIGH or HIGH to LOW after the input logic levels change. The default value is 1.2e-07 s.

Ports

The block has the following ports:

A

Electrical input port.

B

Electrical input port.

J

Electrical output port.

CMOS NOT

CMOS XOR

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